Volume 2 System Programming (794096), страница 64
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If this bit is cleared to 0, the page fault was caused by a not-present page. If this bit is setto 1, the page fault was caused by a page-protection violation.R/W—Bit 1. If this bit is cleared to 0, the access that caused the page fault is a memory read. If thisbit is set to 1, the memory access that caused the page fault was a write. This bit does notnecessarily indicate the cause of the page fault was a read or write violation.Exceptions and Interrupts223AMD64 Technology•••24593—Rev.
3.13—July 2007U/S—Bit 2. If this bit is cleared to 0, an access in supervisor mode (CPL=0, 1, or 2) caused thepage fault. If this bit is set to 1, an access in user mode (CPL=3) caused the page fault. This bit doesnot necessarily indicate the cause of the page fault was a privilege violation.RSV—Bit 3. If this bit is set to 1, the page fault is a result of the processor reading a 1 from areserved field within a page-translation-table entry.
This type of page fault occurs only whenCR4.PSE=1 or CR4.PAE=1. If this bit is cleared to 0, the page fault was not caused by theprocessor reading a 1 from a reserved field.I/D—Bit 4. If this bit is set to 1, it indicates that the access that caused the page fault was aninstruction fetch.
Otherwise, this bit is cleared to 0. This bit is only defined if no-execute feature isenabled (EFER.NXE=1 && CR4.PAE=1).8.5PrioritiesTo allow for consistent handling of multiple-interrupt conditions, simultaneous interrupts areprioritized by the processor.
The AMD64 architecture defines priorities between groups of interrupts,and interrupt prioritization within a group is implementation dependent. Table 8-8 on page 224 showsthe interrupt priorities defined by the AMD64 architecture.When simultaneous interrupts occur, the processor transfers control to the highest-priority interrupthandler. Lower-priority interrupts from external sources are held pending by the processor, and theyare handled after the higher-priority interrupt is handled. Lower-priority interrupts that result frominternal sources are discarded.
Those interrupts reoccur when the high-priority interrupt handlercompletes and transfers control back to the interrupted instruction. Software interrupts are discarded aswell, and reoccur when the software-interrupt instruction is restarted.Table 8-8.Simultaneous Interrupt PrioritiesInterruptPriority(High)0Interrupt ConditionInterruptVectorProcessor Reset—Machine-Check Exception18External Processor Initialization (INIT)1SMI Interrupt—External Clock Stop (Stpclk)2Single-Step Execution Instruction Trap (rFLAGS.TF=1)3Non-Maskable Interrupt4Maskable External Interrupt (INTR)5224Data, and I/O Breakpoint (Debug Register)1232—255Instruction Breakpoint (Debug Register)1Code-Segment-Limit Violation13Instruction-Fetch Page Fault14Exceptions and Interrupts24593—Rev. 3.13—July 2007Table 8-8.Simultaneous Interrupt Priorities (continued)InterruptPriority67AMD64 TechnologyInterrupt ConditionInterruptVectorInvalid Opcode Exception6Device-Not-Available Exception7Instruction-Length Violation (> 15 Bytes)13Divide-by-zero Exception0Invalid-TSS Exception10Segment-Not-Present Exception11Stack Exception12General-Protection Exception13Data-Access Page Fault14Floating-Point Exception-Pending Exception16Alignment-Check Exception17SIMD Floating-Point Exception198.5.1 Floating-Point Exception PrioritiesFloating-point exceptions (128-bit media and x87 floating-point) can be handled in one of two ways:••Unmasked exceptions are reported in the appropriate floating-point status register, and a softwareinterrupt handler is invoked.
See “#MF—x87 Floating-Point Exception-Pending (Vector 16)” onpage 218 and “#XF—SIMD Floating-Point Exception (Vector 19)” on page 221 for moreinformation on the floating-point interrupts.Masked exceptions are also reported in the appropriate floating-point status register. Instead oftransferring control to an interrupt handler, however, the processor handles the exception in adefault manner and execution proceeds.If the processor detects more than one exception while executing a single floating-point instruction, itprioritizes the exceptions in a predictable manner. When responding in a default manner to maskedexceptions, it is possible that the processor acts only on the high-priority exception and ignores lowerpriority exceptions. In the case of vector (SIMD) floating-point instructions, priorities are set on suboperations, not across all operations.
For example, if the processor detects and acts on a QNaN operandin one sub-operation, the processor can still detect and act on a denormal operand in another suboperation.When reporting 128-bit media floating-point exceptions before taking an interrupt or handling them ina default manner, the processor first classifies the exceptions as follows:••Input exceptions include SNaN operand (#I), invalid operation (#I), denormal operand (#D), orzero-divide (#Z). Using a NaN operand with a maximum, minimum, compare, or convertinstruction is also considered an input exception.Output exceptions include numeric overflow (#O), numeric underflow (#U), and precision (#P).Exceptions and Interrupts225AMD64 Technology24593—Rev.
3.13—July 2007Using the above classification, the processor applies the following procedure to report the exceptions:1. The exceptions for all sub-operations are prioritized.2. The exception conditions for all sub-operations are logically ORed together to form a single set ofexceptions covering all operations. For example, if two sub-operations produce a denormal result,only one denormal exception is reported.3. If the set of exceptions includes any unmasked input exceptions, all input exceptions are reportedin MCXSR, and no output exceptions are reported.
Otherwise, all input and output exceptions arereported in MCXSR.4. If any exceptions are unmasked, control is transferred to the appropriate interrupt handler.Table 8-9 on page 226 lists the priorities for simultaneous floating-point exceptions.Table 8-9.Simultaneous Floating-Point Exception PrioritiesExceptionPriorityException ConditionSNaN Operand(High)0NaN Operand of Maximum, Minimum, Compare, andConvert Instructions (Vector Floating-Point)#IStack Overflow (x87 Floating-Point)Stack Underflow (x87 Floating-Point)12345(Low)QNaN Operand—Invalid Operation (Remaining Conditions)#IZero Divide#ZDenormal Operand#DNumeric Overflow#ONumeric Underflow#UPrecision#P8.5.2 External Interrupt PrioritiesThe AMD64 architecture allows software to define up to 15 external interrupt-priority classes. Priorityclasses are numbered from 1 to 15, with priority-class 1 being the lowest and priority-class 15 thehighest.
The organization of these priority classes is implementation dependent. A typical method is touse the upper four bits of the interrupt vector number to define the priority. Thus, interrupt vector 53hhas a priority of 5 and interrupt vector 37h has a priority of 3.A new control register (CR8) is introduced by the AMD64 architecture for managing priority classes.This register, called the task-priority register (TPR), uses its four low-order bits to specify a taskpriority. The remaining 60 bits are reserved and must be written with zeros. Figure 8-4 shows theformat of the TPR.226Exceptions and Interrupts24593—Rev. 3.13—July 2007AMD64 TechnologyThe TPR is available only in 64-bit mode.634Reserved, MBZFigure 8-4.30Task Priority(TPR)Task Priority Register (CR8)System software can use the TPR register to temporarily block low-priority interrupts frominterrupting a high-priority task.
This is accomplished by loading TPR with a value corresponding tothe highest-priority interrupt that is to be blocked. For example, loading TPR with a value of 9 (1001b)blocks all interrupts with a priority class of 9 or less, while allowing all interrupts with a priority classof 10 or more to be recognized. Loading TPR with 0 enables all external interrupts. Loading TPR with15 (1111b) disables all external interrupts. The TPR is cleared to 0 on reset.System software reads and writes the TPR using a MOV CR8 instruction.
The MOV CR8 instructionrequires a privilege level of 0. Programs running at any other privilege level cannot read or write theTPR, and an attempt to do so results in a general-protection exception (#GP).A serializing instruction is not required after loading the TPR, because a new priority level isestablished when the MOV instruction completes execution. For example, assume two sequential TPRloads are performed, in which a low value is first loaded into TPR and immediately followed by a loadof a higher value.
Any pending, lower-priority interrupt enabled by the first MOV CR8 is recognizedbetween the two MOVs.The TPR is an architectural abstraction of the interrupt controller (IC), which prioritizes and managesexternal interrupt delivery to the processor. The IC can be an external system device, or it can beintegrated on the chip like the local advanced programmable interrupt controller (APIC). Typically, theIC contains a priority mechanism similar, if not identical to, the TPR. The IC, however, isimplementation dependent, and the underlying priority mechanisms are subject to change. The TPR,by contrast, is part of the AMD64 architecture.Effect of IC on TPR.
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