Volume 2 System Programming (794096), страница 59
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IORRBasen RegisterIORRMaskn Registers. The fields in these IORRs are:••Valid (V)—Bit 11. Indicates that the IORR pair is valid (enabled) when set to 1. When the valid bitis cleared to 0 the register pair is not used for memory-mapped I/O control (disabled).Range Physical-Mask (PhysMask)—Bits 51–12. The mask value used to specify the memoryrange. Like PhysBase, PhysMask is aligned on a 4-Kbyte physical-address boundary. Bits 11–0 ofPhysMask are assumed to be 0.The format of these registers is shown in Figure 7-13.198Memory System24593—Rev. 3.13—July 200763AMD64 Technology52 5132PhysMaskReserved, MBZ(This is an architectural limit.
A given implementation may support fewer bits.)3112 11 10PhysMaskBits63-5251-121110-0MnemonicReservedPhysMaskVReservedDescriptionReserved, Must be ZeroRange Physical MaskI/O Register Pair Enable (Valid)Reserved, Must be ZeroV0Reserved, MBZR/WR/WR/WFigure 7-13. IORRMaskn RegisterThe operation of the PhysMask and PhysBase fields is identical to that of the variable-range MTRRs.See page 186 for a description of this operation.7.9.3 IORR OverlappingThe use of overlapping IORRs is not recommended.
If overlapping IORRs are specified, the resultingbehavior is implementation-dependent.7.9.4 Top of MemoryThe top-of-memory registers, TOP_MEM and TOP_MEM2, allow system software to specify physicaladdresses ranges as memory-mapped I/O locations. Processor implementations can direct accesses tomemory-mapped I/O differently than system I/O, and the precise method depends on theimplementation. System software specifies memory-mapped I/O regions by writing an address intoeach of the top-of-memory registers. The memory regions specified by the TOP_MEM registers arealigned on 8-Mbyte boundaries as follows:••••Memory accesses from physical address 0 to one less than the value in TOP_MEM are directed tosystem memory.Memory accesses from the physical address specified in TOP_MEM to FFFF_FFFFh are directedto memory-mapped I/O.Memory accesses from physical address 1_0000_0000h to one less than the value in TOP_MEM2are directed to system memory.Memory accesses from the physical address specified in TOP_MEM2 to the maximum physicaladdress supported by the system are directed to memory-mapped I/O.Figure 7-14 on page 200 shows how the top-of-memory registers organize memory into separatesystem-memory and memory-mapped I/O regions.Memory System199AMD64 Technology24593—Rev.
3.13—July 2007The intersection of the top-of-memory range with the equivalent effective MTRR range follows thesame type encoding table (Table 7-11 on page 197) as the fixed-range MTRR, where theRdMem/WrMem and memory type are directly tied together.Physical MemoryMaximum System MemoryMemory-MappedI/OTOP_MEM2TOP_MEM2 - 1System MemoryMemory-MappedI/O4GB4GB - 1TOP_MEMTOP_MEM - 1System Memory0513-269.epsFigure 7-14. Memory Organization Using Top-of-Memory RegistersFigure 7-15 on page 200 shows the format of the TOP_MEM and TOP_MEM2 registers. Bits 51–23specify an 8-Mbyte aligned physical address. All remaining bits are reserved and ignored by theprocessor. System software should clear those bits to zero to maintain compatibility with possiblefuture extensions to the registers.
The TOP_MEM registers are model-specific registers. See“Memory-Typing MSRs” on page 458 for information on the MSR address and reset values for theseregisters.6352 51Top-of-Memory Physical Address(This is an architectural limit. A given implementation may support fewer bits.)Reserved, IGN3123 22Top-of-Memory Physical AddressFigure 7-15.200320Reserved, IGNTop-of-Memory Registers (TOP_MEM, TOP_MEM2)Memory System24593—Rev. 3.13—July 2007AMD64 TechnologyThe TOP_MEM register is enabled by setting the MtrrVarDramEn bit in the SYSCFG MSR (bit 20) to1.
The TOP_MEM2 register is enabled by setting the MtrrTom2En bit in the SYSCFG MSR (bit 21) to1. The registers are disabled when their respective enable bits are cleared to 0. When the top-ofmemory registers are disabled, memory accesses default to memory-mapped I/O space.Memory System201AMD64 Technology20224593—Rev. 3.13—July 2007Memory System24593—Rev. 3.13—July 20078AMD64 TechnologyExceptions and InterruptsExceptions and interrupts force control transfers from the currently-executing program to a systemsoftware service routine that handles the interrupting event. These routines are referred to as exceptionhandlers and interrupt handlers, or collectively as event handlers.
Typically, interrupt events can behandled by the service routine transparently to the interrupted program. During the control transfer tothe service routine, the processor stops executing the interrupted program and saves its return pointer.The system-software service routine that handles the exception or interrupt is responsible for savingthe state of the interrupted program. This allows the processor to restart the interrupted program aftersystem software has handled the event.When an exception or interrupt occurs, the processor uses the interrupt-vector number as an index intothe interrupt-descriptor table (IDT). An IDT is used in all processor operating modes, including realmode (also called real-address mode), protected mode, and long mode.Exceptions and interrupts come from three general sources:•••Exceptions occur as a result of software execution errors or other internal-processor errors.Exceptions also occur during non-error situations, such as program single stepping or addressbreakpoint detection.
Exceptions are considered synchronous events because they are a directresult of executing the interrupted instruction.Software interrupts occur as a result of executing interrupt instructions. Unlike exceptions andexternal interrupts, software interrupts allow intentional triggering of the interrupt-handlingmechanism. Like exceptions, software interrupts are synchronous events.External interrupts are generated by system logic in response to an error or some other eventoutside the processor. They are reported over the processor bus using external signalling. Externalinterrupts are asynchronous events that occur independently of the interrupted instruction.Throughout this section, the term masking can refer to either disabling or delaying an interrupt.
Forexample, masking external interrupts delays the interrupt, with the processor holding the interrupt aspending until it is unmasked. With floating-point exceptions (128-bit media and x87), maskingprevents an interrupt from occurring and causes the processor to perform a default operation on theexception condition.8.1General CharacteristicsExceptions and interrupts have several different characteristics that depend on how events are reportedand the implications for program restart.8.1.1 PrecisionPrecision describes how the exception is related to the interrupted program:•Precise exceptions are reported on a predictable instruction boundary. This boundary is generallythe first instruction that has not completed when the event occurs. All previous instructions (inExceptions and Interrupts203AMD64 Technology•24593—Rev.
3.13—July 2007program order) are allowed to complete before transferring control to the event handler. Thepointer to the instruction boundary is saved automatically by the processor. When the event handlercompletes execution, it returns to the interrupted program and restarts execution at the interruptedinstruction boundary.Imprecise exceptions are not guaranteed to be reported on a predictable instruction boundary. Theboundary can be any instruction that has not completed when the interrupt event occurs.
Impreciseevents can be considered asynchronous, because the source of the interrupt is not necessarilyrelated to the interrupted instruction. Imprecise exception and interrupt handlers typically collectmachine-state information related to the interrupting event for reporting through system-diagnosticsoftware. The interrupted program is not restartable.8.1.2 Instruction RestartAs mentioned above, precise exceptions are reported on an instruction boundary. The instructionboundary can be reported in one of two locations:••Most exceptions report the boundary before the instruction causing the exception. In this case, allprevious instructions (in program order) are allowed to complete, but the interrupted instruction isnot.
No program state is updated as a result of partially executing an interrupted instruction.Some exceptions report the boundary after the instruction causing the exception. In this case, allprevious instructions—including the one executing when the exception occurred—are allowed tocomplete.Program state can be updated when the reported boundary is after the instruction causing theexception. This is particularly true when the event occurs as a result of a task switch.
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