Volume 2 System Programming (794096), страница 60
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In this case,the general registers, segment-selector registers, page-base address register, and LDTR are allupdated by the hardware task-switch mechanism. The event handler cannot rely on the state ofthose registers when it begins execution and must be careful in validating the state of the segmentselector registers before restarting the interrupted task. This is not an issue in long mode, however,because the hardware task-switch mechanism is disabled in long mode.8.1.3 Types of ExceptionsThere are three types of exceptions, depending on whether they are precise and how they affectprogram restart:•••Faults are precise exceptions reported on the boundary before the instruction causing theexception.
Generally, faults are caused by an error condition involving the faulted instruction. Anymachine-state changes caused by the faulting instruction are discarded so that the instruction canbe restarted. The saved rIP points to the faulting instruction.Traps are precise exceptions reported on the boundary following the instruction causing theexception. The trapped instruction is completed by the processor and all state changes are saved.The saved rIP points to the instruction following the faulting instruction.Aborts are imprecise exceptions.
Because they are imprecise, aborts typically do not allow reliableprogram restart.204Exceptions and Interrupts24593—Rev. 3.13—July 2007AMD64 Technology8.1.4 Masking External InterruptsGeneral Masking Capabilities. Software can mask the occurrence of certain exceptions andinterrupts. Masking can delay or even prevent triggering of the exception-handling or interrupthandling mechanism when an interrupt-event occurs. External interrupts are classified as maskable ornonmaskable:••Maskable interrupts trigger the interrupt-handling mechanism only when RFLAGS.IF=1.Otherwise they are held pending for as long as the RFLAGS.IF bit is cleared to 0.Nonmaskable interrupts (NMI) are unaffected by the value of the rFLAGS.IF bit. However, theoccurrence of an NMI masks further NMIs until an IRET instruction is executed.Masking During Stack Switches.
The processor delays recognition of maskable external interruptsand debug exceptions during certain instruction sequences that are often used by software to switchstacks. The typical programming sequence used to switch stacks is:1. Load a stack selector into the SS register.2. Load a stack offset into the ESP register.If an interrupting event occurs after the selector is loaded but before the stack offset is loaded, theinterrupted-program stack pointer is invalid during execution of the interrupt handler.To prevent interrupts from causing stack-pointer problems, the processor does not allow externalinterrupts or debug exceptions to occur until the instruction immediately following the MOV SS orPOP SS instruction completes execution.The recommended method of performing this sequence is to use the LSS instruction. LSS loads bothSS and ESP, and the instruction inhibits interrupts until both registers are updated successfully.8.1.5 Masking Floating-Point and Media InstructionsAny x87 floating-point exceptions can be masked and reported later using bits in the x87 floating-pointstatus register (FSW) and the x87 floating-point control register (FCW).
The floating-point exceptionpending exception is used for unmasked x87 floating-point exceptions (see “#MF—x87 FloatingPoint Exception-Pending (Vector 16)” on page 218).The SIMD floating-point exception is used for unmasked 128-bit media floating-point exceptions (see“#XF—SIMD Floating-Point Exception (Vector 19)” on page 221). 128-bit media floating-pointexceptions are masked using the MXCSR register.
The exception mechanism is not triggered whenthese exceptions are masked. Instead, the processor handles the exceptions in a default manner.8.1.6 Disabling ExceptionsDisabling an exception prevents the exception condition from being recognized, unlike masking anexception which prevents triggering the exception mechanism after the exception is recognized. Someexceptions can be disabled by system software running at CPL=0, using bits in the CR0 register orCR4 register:Exceptions and Interrupts205AMD64 Technology24593—Rev. 3.13—July 2007••Alignment-check exception (see “#AC—Alignment-Check Exception (Vector 17)” on page 219).Device-not-available exception (see “#NM—Device-Not-Available Exception (Vector 7)” onpage 212).•Machine-check exception (see “#MC—Machine-Check Exception (Vector 18)” on page 220).The debug-exception mechanism provides control over when specific breakpoints are enabled anddisabled.
See “Breakpoints” on page 333 for more information on how breakpoint controls are usedfor triggering the debug-exception mechanism.8.2VectorsSpecific exception and interrupt sources are assigned a fixed vector-identification number (also calledan “interrupt vector” or simply “vector”). The interrupt vector is used by the interrupt-handlingmechanism to locate the system-software service routine assigned to the exception or interrupt. Up to256 unique interrupt vectors are available.
The first 32 vectors are reserved for predefined exceptionand interrupt conditions. Software-interrupt sources can trigger an interrupt using any availableinterrupt vector.Table 8-1 on page 207 lists the supported interrupt-vector numbers, the corresponding exception orinterrupt name, the mnemonic, the source of the interrupt event, and a summary of the possible causes.206Exceptions and Interrupts24593—Rev. 3.13—July 2007Table 8-1.AMD64 TechnologyInterrupt-Vector Source and CauseVectorException/InterruptMnemonicCause0Divide-by-Zero-Error#DEDIV, IDIV, AAM instructions1Debug#DBInstruction accesses and data accesses2Non-Maskable-Interrupt#NMIExternal NMI signal3Breakpoint#BPINT3 instruction4Overflow#OFINTO instruction5Bound-Range#BRBOUND instruction6Invalid-Opcode#UDInvalid instructions7Device-Not-Available#NMx87 instructions8Double-Fault#DFException during the handling of anotherexception or interrupt9Coprocessor-Segment-Overrun10Invalid-TSS#TSTask-state segment access and task switch11Segment-Not-Present#NPSegment register loads12Stack#SSSS register loads and stack references13General-Protection#GPMemory accesses and protection checks14Page-Fault#PFMemory accesses when paging enabled15Reserved16x87 Floating-Point ExceptionPending#MFx87 floating-point instructions17Alignment-Check#ACMisaligned memory accesses18Machine-Check#MCModel specific19SIMD Floating-Point#XF128-bit media floating-point instructions—Unsupported (Reserved)—20—29 Reserved30Security Exception31Reserved0—255 External Interrupts (Maskable)0—255 Software Interrupts—#SXSecurity-sensitive event in host—#INTR—External interruptsINTn instructionTable 8-2 on page 208 shows how each interrupt vector is classified.
Reserved interrupt vectors areindicated by the gray-shaded rows.Exceptions and Interrupts207AMD64 Technology24593—Rev. 3.13—July 2007Table 8-2. Interrupt-Vector ClassificationVectorInterrupt (Exception)TypeFaultPreciseClass20Divide-by-Zero-Error1Debug2Non-Maskable-Interrupt3Breakpoint4Overflow5Bound-Range6Invalid-Opcode7Device-Not-Available8Double-Fault9Coprocessor-Segment-Overrun10Invalid-TSS11Segment-Not-Present12Stack13General-Protection14Page-Fault15Reserved16x87 Floating-Point ExceptionPending17Alignment-Check18Machine-CheckAbortno19SIMD Floating-PointFaultyes–yesContributory—1—1BenignFault or Trap—yesContributory—TrapyesBenignFaultAbortnoFaultyesContributoryBenign orContributoryFaultnoyesBenign20—29 Reserved30Security Exception31Reserved0—255 External Interrupts (Maskable)0—255 Software InterruptsNote:1. External interrupts are not classified by type or whether or not they are precise.2.
See “#DF—Double-Fault Exception (Vector 8)” on page 212 for a definition of benign and contributory classes.The following sections describe each interrupt in detail. The format of the error code reported by eachinterrupt is described in “Error Codes” on page 222.208Exceptions and Interrupts24593—Rev. 3.13—July 2007AMD64 Technology8.2.1 #DE—Divide-by-Zero-Error Exception (Vector 0)A #DE exception occurs when the denominator of a DIV instruction or an IDIV instruction is 0. A#DE also occurs if the result is too large to be represented in the destination.#DE cannot be disabled.Error Code Returned.
None.Program Restart. #DE is a fault-type exception. The saved instruction pointer points to theinstruction that caused the #DE.8.2.2 #DB—Debug Exception (Vector 1)When the debug-exception mechanism is enabled, a #DB exception can occur under any of thefollowing circumstances:•••••••••Instruction execution.Instruction single stepping.Data read.Data write.I/O read.I/O write.Task switch.Debug-register access, or general detect fault (debug register access when DR7.GD=1).Executing the INT1 instruction (opcode 0F1h).#DB conditions are enabled and disabled using the debug-control register, DR7 and RFLAGS.TF.Each #DB condition is described in more detail in “Breakpoints” on page 333.Error Code Returned. None. #DB information is returned in the debug-status register, DR6.Program Restart.
#DB can be either a fault-type or trap-type exception. In the following cases, thesaved instruction pointer points to the instruction that caused the #DB:••Instruction execution.Invalid debug-register access, or general detect.In all other cases, the instruction that caused the #DB is completed, and the saved instruction pointerpoints to the instruction after the one that caused the #DB.The RFLAGS.RF bit can be used to restart an instruction following an instruction breakpoint resultingin a #DB. In most cases, the processor clears RFLAGS.RF to 0 after every instruction is successfullyexecuted. However, in the case of the IRET, JMP, CALL, and INTn (through a task gate) instructions,RFLAGS.RF is not cleared to 0 until the next instruction successfully executes.Exceptions and Interrupts209AMD64 Technology24593—Rev.
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