Volume 2 System Programming (794096), страница 57
Текст из файла (страница 57)
Clearing E to 0 disables all fixed-range and variable-rangeMTRRs and sets the default memory-type to uncacheable (UC) regardless of the value of the Typefield.7.7.3 Using MTRRsIdentifying MTRR Features. Software determines whether a processor supports the MTRRmechanism by executing the CPUID instruction with either function 1 or function 8000_0001h. IfMTRRs are supported, bit 12 in the EDX register is set to 1 by CPUID. See “Processor FeatureIdentification” on page 61 for more information on the CPUID instruction.The MTRR capability register (MTRRcap) is a read-only register containing information describingthe level of MTRR support provided by the processor.
Figure 7-9 shows the format of this register. IfMTRRs are supported, software can read MTRRcap using the RDMSR instruction. Attempting towrite to the MTRRcap register causes a general-protection exception (#GP).6332Reserved3111 10 9 8R FWe ICs XReservedBits63-1110987-0MnemonicReservedWCReservedFIXVCNTDescriptionReservedWrite CombiningReservedFixed-Range RegistersVariable-Range Register Count70VCNTR/WRRRFigure 7-9. MTRR Capability Register Format188Memory System24593—Rev.
3.13—July 2007AMD64 TechnologyThe MTRRcap register field are:•••Variable-Range Register Count (VCNT)—Bits 7–0. The VCNT field contains the number ofvariable-range register pairs supported by the processor. For example, a processor supporting eightregister pairs returns a 08h in this field.Fixed-Range Registers (FIX)—Bit 8. The FIX bit indicates whether or not the fixed-range registersare supported. If the processor returns a 1 in this bit, all fixed-range registers are supported.
If theprocessor returns a 0 in this bit, no fixed-range registers are supported.Write-Combining (WC)—Bit 10. The WC bit indicates whether or not the write-combiningmemory type is supported. If the processor returns a 1 in this bit, WC memory is supported,otherwise it is not supported.7.7.4 MTRRs and Page Cache ControlsWhen paging and the MTRRs are both enabled, the address ranges defined by the MTRR registers canspan multiple pages, each of which can characterize memory with different types (using the PCD andPWT page bits).
When caching is enabled (CR0.CD=0 and CR0.NW=0), the effective memory-type isdetermined as follows:1. If the page is defined as cacheable and writeback (PCD=0 and PWT=0), then the MTRR definesthe effective memory-type.2. If the page is defined as not cacheable (PCD=1), then UC is the effective memory-type.3. If the page is defined as cacheable and writethrough (PCD=0 and PWT=1), then the MTRRdefines the effective memory-type unless the MTRR specifies WB memory, in which case WT isthe effective memory-type.Table 7-7 lists the MTRR and page-level cache-control combinations and their combined effect on thefinal memory-type, if the PAT register holds the default settings.Table 7-7.Combined MTRR and Page-Level Memory Type withUnmodified PAT MSRMTRRMemory TypePagePCD BitPagePWT BitEffectiveMemory-TypeUC——UC0—WC10WC111UC0—WP1—UCWCWPNote:1.
The effective memory-type resulting from the combination of PCD=1, PWT=0, andan MTRR WC memory type is implementation dependent.Memory System189AMD64 TechnologyTable 7-7.24593—Rev. 3.13—July 2007Combined MTRR and Page-Level Memory Type withUnmodified PAT MSR (continued)MTRRMemory TypeWTWBPagePCD BitPagePWT BitEffectiveMemory-Type0—WT1—UC00WB01WT1—UCNote:1. The effective memory-type resulting from the combination of PCD=1, PWT=0, andan MTRR WC memory type is implementation dependent.Large Page Sizes. When paging is enabled, software can use large page sizes (2 Mbytes and4 Mbytes) in addition to the more typical 4-Kbyte page size.
When large page sizes are used, it ispossible for multiple MTRRs to span the memory range within a single large page. Each MTRR cancharacterize the regions within the page with different memory types. If this occurs, the effectivememory-type used by the processor within the large page is undefined.Software can avoid the undefined behavior in one of the following ways:••••Avoid using multiple MTRRs to characterize a single large page.Use multiple 4-Kbyte pages rather than a single large page.If multiple MTRRs must be used within a single large page, software can set the MTRR type fieldsto the same value.If the multiple MTRRs must have different type-field values, software can set the large page PCDand PWT bits to the most restrictive memory type defined by the multiple MTRRs.Overlapping MTRR Registers.
If the address ranges of two or more MTRRs overlap, the followingrules are applied to determine the memory type used to characterize the overlapping address range:1. Fixed-range MTRRs, which characterize only the first 1 Mbyte of physical memory, haveprecedence over variable-range MTRRs.2. If two or more variable-range MTRRs overlap, the following rules apply:a — If the memory types are identical, then that memory type is used.b. If at least one of the memory types is UC, the UC memory type is used.c. If at least one of the memory types is WT, and the only other memory type is WB, then theWT memory type is used.d.
If the combination of memory types is not listed Steps A through C immediately above, thenthe memory type used is undefined.190Memory System24593—Rev. 3.13—July 2007AMD64 Technology7.7.5 MTRRs in Multi-Processing EnvironmentsIn multi-processing environments, the MTRRs located in all processors must characterize memory inthe same way. Generally, this means that identical values are written to the MTRRs used by theprocessors.
This also means that values CR0.CD and the PAT must be consistent across processors.Failure to do so may result in coherency violations or loss of atomicity. Processor implementations donot check the MTRR settings in other processors to ensure consistency. It is the responsibility ofsystem software to initialize and maintain MTRR consistency across all processors.7.8Page-Attribute Table MechanismThe page-attribute table (PAT) mechanism extends the page-table entry format and enhances thecapabilities provided by the PCD and PWT page-level cache controls.
PAT (and PCD, PWT) allowmemory-type characterization based on the virtual (linear) address. The PAT mechanism provides thesame memory-typing capabilities as the MTRRs but with the added flexibility of the pagingmechanism. Software can use both the PAT and MTRR mechanisms to maximize flexibility inmemory-type control.7.8.1 PAT RegisterLike the MTRRs, the PAT register is a 64-bit model-specific register (MSR). The format of the PATregisters is shown in Figure 7-10.
See “Memory-Typing MSRs” on page 458 for more information onthe PAT MSR number and reset value.6359 58Reserved3156 55PA727 26Reserved51 50Reserved24 23PA348 47PA619 18Reserved43 42Reserved16 15PA240 41PA511 10ReservedReserved8PA135 347PA43Reserved3220PA0Figure 7-10. PAT RegisterThe PAT register contains eight page-attribute (PA) fields, numbered from PA0 to PA7. The PA fieldshold the encoding of a memory type, as found in Table 7-8 on page 192. The PAT type-encodingsmatch the MTRR type-encodings, with the exception that PAT adds the 07h encoding.
The 07hencoding corresponds to a UC- type. The UC- type (07h) is identical to the UC type (00h) except it canbe overridden by an MTRR type of WC.Software can write any supported memory-type encoding into any of the eight PA fields. An attempt towrite anything but zeros into the reserved fields causes a general-protection exception (#GP). Anattempt to write an unsupported type encoding into a PA field also causes a #GP exception.Memory System191AMD64 Technology24593—Rev. 3.13—July 2007The PAT register fields are initiated at processor reset to the default values shown in Table 7-9 onpage 193.Table 7-8.PAT Type EncodingsType ValueType NameType Description00hUC—Uncacheable01hWC—Write-Combining04hWT—WritethroughReads allocate cache lines on a cache miss, but only to the sharedstate.
Cache lines are not allocated on a write miss. Write hitsupdate the cache and main memory.05hWP—Write-ProtectReads allocate cache lines on a cache miss, but only to the sharedstate. All writes update main memory. Cache lines are not allocatedon a write miss. Write hits invalidate the cache line and update mainmemory.06hWB—WritebackReads allocate cache lines on a cache miss, and can allocate toeither the shared or exclusive state. Writes allocate to the modifiedstate on a cache miss.07hUC–(UC minus)All accesses are uncacheable. Write combining is not allowed.Speculative accesses are not allowed.All accesses are uncacheable. Write combining is allowed.Speculative reads are allowed.All accesses are uncacheable. Write combining is not allowed.Speculative accesses are not allowed.
Can be overridden by anMTRR with the WC type.7.8.2 PAT IndexingPA fields in the PAT register are selected using three bits from the page-table entries. These bits are:•••PAT (page attribute table)—The PAT bit is bit 7 in 4-Kbyte PTEs; it is bit 12 in 2-Mbyte and 4Mbyte PDEs. Page-table entries that don’t have a PAT bit (PML4 entries, for example) assume PAT= 0.PCD (page cache disable)—The PCD bit is bit 4 in all page-table entries. The PCD from the PTEor PDE is selected depending on the paging mode.PWT (page writethrough)—The PWT bit is bit 3 in all page-table entries. The PWT from the PTEor PDE is selected depending on the paging mode.Table 7-9 on page 193 shows the various combinations of the PAT, PCD, and PWT bits used to select aPA field within the PAT register.
Table 7-9 also shows the default memory-type values established inthe PAT register by the processor after a reset. The default values correspond to the memory typesestablished by the PCD and PWT bits alone in processor implementations that do not support the PATmechanism. In such implementations, the PAT field in page-table entries is reserved and cleared to 0.See “Page-Translation-Table Entry Fields” on page 135 for more information on the page-tableentries.192Memory System24593—Rev. 3.13—July 2007Table 7-9.AMD64 TechnologyPAT-Register PA-Field IndexingPage-Table Entry BitsPATPCDPWTPAT RegisterFieldDefaultMemory Type000PA0WB001PA1WT010PA2UC–1011PA3UC100PA4WB101PA5WT110PA6UC–1111PA7UCNote:1.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
