Volume 2 System Programming (794096), страница 58
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Can be overridden by WC memory type set by an MTRR.7.8.3 Identifying PAT SupportSoftware determines whether a processor supports the PAT mechanism by executing the CPUIDinstruction with either function 1 or function 8000_0001h. If PAT is supported, bit 16 in the EDXregister is set to 1 by CPUID. See “Processor Feature Identification” on page 61 for more informationon the CPUID instruction.If PAT is supported by a processor implementation, it is always enabled. The PAT mechanism cannotbe disabled by software. Software can effectively avoid using PAT by:••Not setting PAT bits in page-table entries to 1.Not modifying the reset values of the PA fields in the PAT register.In this case, memory is characterized using the same types that are used by implementations that do notsupport PAT.7.8.4 PAT AccessesIn implementations that support the PAT mechanism, all memory accesses that are translated throughthe paging mechanism use the PAT index bits to specify a PA field in the PAT register.
The memorytype stored in the specified PA field is applied to the memory access. The process is summarized as:1. A virtual address is calculated as a result of a memory access.2. The virtual address is translated to a physical address using the page-translation mechanism.3. The PAT, PCD and PWT bits are read from the corresponding page-table entry during the virtualaddress to physical-address translation.4. The PAT, PCD and PWT bits are used to select a PA field from the PAT register.5. The memory type is read from the appropriate PA field.6.
The memory type is applied to the physical-memory access using the translated physical address.Memory System193AMD64 Technology24593—Rev. 3.13—July 2007Page-Translation Table Access. The PAT bit exists only in the PTE (4-K paging) or PDEs (2/4Mbyte paging). In the remaining upper levels (PML4 PDP, 4K PDEs), only the PWT and PCD bits areused to index into the first 4 entries in the PAT register.
The resulting memory type is used for the nextlower paging level.7.8.5 Combined Effect of MTRRs and PATThe memory types established by the PAT mechanism can be combined with MTRR-establishedmemory types to form an effective memory-type. The combined effect of MTRR and PAT memorytypes are shown in Figure 7-10.
In the AMD64 architecture, reserved and undefined combinations ofMTRR and PAT memory types result in undefined behavior. If the MTRRs are disabled inimplementations that support the MTRR mechanism, the default memory type is set to uncacheable(UC).Table 7-10. Combined Effect of MTRR and PAT Memory TypesPAT Memory TypeMTRR Memory TypeEffective Memory TypeUCUC, WC, WP, WT, WBUCUCUCWCWCWP, WT, WBUC1—WCUCUCWCUC1WPWPWTUC1WBWPUCUCWC, WPUC1WT, WBWTUCUCWCWCWPWPWTWTWBWBUCWCWPWTWBNote:1.
Previously reserved (undefined) combinations are set to the UC memory type bythe AMD64 architecture.194Memory System24593—Rev. 3.13—July 2007AMD64 Technology7.8.6 PATs in Multi-Processing EnvironmentsIn multi-processing environments, values of CR0.CD and the PAT must be consistent across allprocessors and the MTRRs located in all processors must characterize memory in the same way(identical values are written to the MTRRs used by the processors). Failure to do so may result incoherency violations or loss of atomicity.
Processor implementations do not check the MTRR,CR0.CD and PAT values in other processors to ensure consistency. It is the responsibility of systemsoftware to initialize and maintain consistency across all processors.7.9Memory-Mapped I/OProcessor implementations can independently direct reads and writes to either system memory ormemory-mapped I/O. The method used for directing those memory accesses is implementationdependent. In some implementations, separate system-memory and memory-mapped I/O buses can beprovided at the processor interface.
In other implementations, system memory and memory-mappedI/O share common data and address buses, and system logic uses sideband signals from the processorto route accesses appropriately. Refer to AMD data sheets and application notes for more informationabout particular hardware implementations of the AMD64 architecture.The I/O range registers (IORRs), and the top-of-memory registers allow system software to specifywhere memory accesses are directed for a given address range. The MTRR extensions are described inthe following section.
“IORRs” on page 197 describes the IORRs and “Top of Memory” on page 199describes the top-of-memory registers. In implementations that support these features, the defaultaction taken when the features are disabled is to direct memory accesses to memory-mapped I/O.7.9.1 Extended Fixed-Range MTRR Type-Field EncodingsThe fixed-range MTRRs support extensions to the type-field encodings that allow system software todirect memory accesses to system memory or memory-mapped I/O.
The extended MTRR type-fieldencodings use previously reserved bits 4–3 to specify whether reads and writes to a physical-addressrange are to system memory or to memory-mapped I/O. The format for this encoding is shown inFigure 7-11 on page 196. The new bits are:••WrMem—Bit 3. When set to 1, the processor directs write requests for this physical address rangeto system memory. When cleared to 0, writes are directed to memory-mapped I/O.RdMem—Bit 4. When set to 1, the processor directs read requests for this physical address range tosystem memory. When cleared to 0, reads are directed to memory-mapped I/O.The type subfield (bits 2–0) allows the encodings specified in Table 7-5 on page 182 to be used formemory characterization.Memory System195AMD64 Technology24593—Rev. 3.13—July 200775Reserved43RdMemWrMem20TypeFigure 7-11. Extended MTRR Type-Field Format (Fixed-Range MTRRs)These extensions are enabled using the following bits in the SYSCFG MSR:••MtrrFixDramEn—Bit 18.
When set to 1, RdMem and WrMem attributes are enabled. Whencleared to 0, these attributes are disabled. When disabled, accesses are directed to memory-mappedI/O space.MtrrFixDramModEn—Bit 19. When set to 1, software can read and write the RdMem andWrMem bits. When cleared to 0, writes do not modify the RdMem and WrMem bits, and readsreturn 0.To use the MTRR extensions, system software must first set MtrrFixDramModEn=1 to allowmodification to the RdMem and WrMem bits. After the attribute bits are properly initialized in thefixed-range registers, the extensions can be enabled by setting MtrrFixDramEn=1.RdMem and WrMem allow the processor to independently direct reads and writes to either systemmemory or memory-mapped I/O. The RdMem and WrMem controls are particularly useful whenshadowing ROM devices located in memory-mapped I/O space.
It is often useful to shadow suchdevices in RAM system memory to improve access performance, but writes into the RAM location cancorrupt the shadowed ROM information. The MTRR extensions solve this problem. System softwarecan create the shadow location by setting WrMem = 1 and RdMem = 0 for the specified memory rangeand then copy the ROM location into itself. Reads are directed to the memory-mapped ROM, butwrites go to the same physical addresses in system memory. After the copy is complete, systemsoftware can change the bit values to WrMem = 0 and RdMem = 1. Now reads are directed to the fastercopy located in system memory, and writes are directed to memory-mapped ROM.
The ROM respondsas it would normally to a write, which is to ignore it.Not all combinations of RdMem and WrMem are supported for each memory type encoded by bits2–0. Table 7-11 on page 197 shows the allowable combinations. The behavior of reserved encodingcombinations (shown as gray-shaded cells) is undefined and results in unpredictable behavior.196Memory System24593—Rev. 3.13—July 2007AMD64 TechnologyTable 7-11. Extended Fixed-Range MTRR Type EncodingsRdMem0WrMem0TypeImplication or Potential Use0 (UC)UC I/O1 (WC)WC I/O4 (WT)WT I/O5 (WP)WP I/O6 (WB)Reserved0 (UC)1 (WC)01Used while creating a shadowed ROM4 (WT)5 (WP)Reserved6 (WB)0 (UC)Used to access a shadowed ROM1 (WC)1101Reserved4 (WT)5 (WP)WP Memory(Can be used to access shadowed ROM)6 (WB)Reserved0 (UC)UC Memory1 (WC)WC Memory4 (WT)WT Memory5 (WP)Reserved6 (WB)WB Memory7.9.2 IORRsThe IORRs operate similarly to the variable-range MTRRs.
The IORRs specify whether reads andwrites in any physical-address range map to system memory or memory-mapped I/O. Up to twoaddress ranges of varying sizes can be controlled using the IORRs. A pair of IORRs are used to controleach address range: IORRBasen and IORRMaskn (n is the address-range number from 0 to 1).Figure 7-12 on page 198 shows the format of the IORRBasen registers and Figure 7-13 on page 199shows the format of the IORRMaskn registers. The fields within the register pair are read/write.The intersection of the IORR range with the equivalent effective MTRR range follows the same typeencoding table (Table 7-11) as the fixed-range MTRR, where the RdMem/WrMem and memory typeare directly tied together.IORRBasen Registers.
The fields in these IORRs are:•WrMem—Bit 3. When set to 1, the processor directs write requests for this physical address rangeto system memory. When cleared to 0, writes are directed to memory-mapped I/O.Memory System197AMD64 Technology••24593—Rev. 3.13—July 2007RdMem—Bit 4. When set to 1, the processor directs read requests for this physical address range tosystem memory. When cleared to 0, reads are directed to memory-mapped I/O.Range Physical-Base-Address (PhysBase)—Bits 51–12. The memory-range base-address inphysical-address space.
PhysBase is aligned on a 4-Kbyte (or greater) address in the 52-bitphysical-address space supported by the AMD64 architecture. PhysBase represents the mostsignificant 40-address bits of the physical address. Physical-address bits 11–0 are assumed to be 0.The format of these registers is shown in Figure 7-12 on page 198.6352 5132PhysBaseReserved, MBZ(This is an architectural limit. A given implementation may support fewer bits.)3112 11PhysBaseBits63-5251-1211-5432-0MnemonicReservedPhysBaseReservedRdWrReservedDescriptionReserved, Must be ZeroRange Physical Base AddressReserved, Must be ZeroRdMem EnableWrMem EnableReserved, Must be Zero5Reserved, MBZ430R W Reserved,MBZd rR/WR/WR/WR/WFigure 7-12.
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