Volume 2 System Programming (794096), страница 56
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They are read using the RDMSR instruction andwritten using the WRMSR instruction. See “Memory-Typing MSRs” on page 458 for a listing of theMTRR MSR numbers. The following sections describe the types of MTRRs and their function.Fixed-Range MTRRs. The fixed-range MTRRs are used to characterize the first 1 Mbyte of physicalmemory. Each fixed-range MTRR contains eight type fields for characterizing a total of eight memoryranges. Fixed-range MTRRs support extended type-field encodings as described in “Extended FixedRange MTRR Type-Field Encodings” on page 195.
The extended type field allows a fixed-rangeMTRR to be used as a fixed-range IORR. Figure 7-5 on page 184 shows the format of a fixed-rangeMTRR.Memory System183AMD64 Technology6324593—Rev. 3.13—July 200756 5548 47Type40 39Type3124 23TypeType16 15Type8Type32Type70TypeFigure 7-5. Fixed-Range MTRRFor the purposes of memory characterization, the first 1 Mbyte of physical memory is segmented intoa total of 88 non-overlapping memory ranges, as follows:•••The 512 Kbytes of memory spanning addresses 00_0000h to 07_FFFFh are segmented into eight64-Kbyte ranges.
A single MTRR is used to characterize this address space.The 256 Kbytes of memory spanning addresses 08_0000h to 0B_FFFFh are segmented into 16 16Kbyte ranges. Two MTRRs are used to characterize this address space.The 256 Kbytes of memory spanning addresses 0C_0000h to 0F_FFFFh are segmented into 64 4Kbyte ranges. Eight MTRRs are used to characterize this address space.Table 7-6 shows the address ranges corresponding to the type fields within each fixed-range MTRR.The gray-shaded heading boxes represent the bit ranges for each type field in a fixed-range MTTR. SeeTable 7-5 on page 182 for the type-field encodings.Table 7-6.Fixed-Range MTRR Address RangesPhysical Address Range (in hexadecimal)Register Name63–5655–4847–4039–3231–2423–1615–87–070000–7FFFF60000–6FFFF50000–5FFFF40000–4FFFF30000–3FFFF20000–2FFFF10000–1FFFF00000–0FFFFMTRRfix64K_000009C000– 98000–9FFFF 9BFFF94000–97FFF90000–93FFF8C000– 88000–8FFFF 8BFFF84000–87FFF80000–83FFFMTRRfix16K_80000BC000– B8000–BFFFF BBFFFB4000–B7FFFB0000–B3FFFAC000– A8000–AFFFF ABFFFA4000–A7FFFA0000–A3FFFMTRRfix16K_A0000C7000– C6000– C5000– C4000– C3000– C2000– C1000– C0000–C7FFF C6FFF C5FFF C4FFF C3FFF C2FFF C1FFF C0FFFMTRRfix4K_C0000CF000– CE000– CD000– CC000– CB000– CA000– C9000– C8000–CFFFF CEFFF CDFFF CCFFF CBFFF CAFFF C9FFF C8FFFMTRRfix4K_C8000D7000– D6000– D5000– D4000– D3000– D2000– D1000– D0000–D7FFF D6FFF D5FFF D4FFF D3FFF D2FFF D1FFF D0FFFMTRRfix4K_D0000DF000– DE000– DD000– DC000– DB000– DA000– D9000– D8000–DFFFF DEFFF DDFFF DCFFF DBFFF DAFFF D9FFF D8FFFMTRRfix4K_D8000E7000–E7FFFMTRRfix4K_E0000184E6000–E6FFFE5000–E5FFFE4000–E4FFFE3000–E3FFFE2000–E2FFFE1000–E1FFFE0000–E0FFFMemory System24593—Rev.
3.13—July 2007Table 7-6.AMD64 TechnologyFixed-Range MTRR Address Ranges (continued)Physical Address Range (in hexadecimal)63–5655–4847–4039–3231–2423–1615–8Register Name7–0EF000– EE000– ED000– EC000– EB000– EA000– E9000–EFFFF EEFFF EDFFF ECFFF EBFFF EAFFF E9FFFE8000–E8FFFMTRRfix4K_E8000F7000–F7FFFF6000–F6FFFF2000–F2FFFF1000–F1FFFF0000–F0FFFMTRRfix4K_F0000FF000–FFFFFFE000– FD000– FC000– FB000– FA000–FEFFF FDFFF FCFFF FBFFF FAFFFF9000–F9FFFF8000–F8FFFMTRRfix4K_F8000F5000–F5FFFF4000–F4FFFF3000–F3FFFVariable-Range MTRRs.
The variable-range MTRRs can be used to characterize any address rangewithin the physical-memory space, including all of physical memory. Up to eight address ranges ofvarying sizes can be characterized using the MTRR. Two variable-range MTRRs are used tocharacterize each address range: MTRRphysBasen and MTRRphysMaskn (n is the address-rangenumber from 0 to 7).
For example, address-range 3 is characterized using the MTRRphysBase3 andMTRRphysMask3 register pair.Figure 7-6 shows the format of the MTRRphysBasen register and Figure 7-7 on page 186 shows theformat of the MTRRphysMaskn register. The fields within the register pair are read/write.MTRRphysBasen Registers. The fields in these variable-range MTRRs, shown in Figure 7-6, are:••Type—Bits 7–0.
The memory type used to characterize the memory range. See Table 7-5 onpage 182 for the type-field encodings. Variable-range MTRRs do not support the extended typefield encodings.Range Physical Base-Address (PhysBase)—Bits 51–12. The memory-range base-address inphysical-address space. PhysBase is aligned on a 4-Kbyte (or greater) address in the 52-bitphysical-address space supported by the AMD64 architecture. PhysBase represents the mostsignificant 40-address bits of the physical address. Physical-address bits 11–0 are assumed to be 0.6352 5132PhysBaseReserved, MBZ(This is an architectural limit.
A given implementation may support fewer bits.)3112 11Reserved,MBZPhysBaseBits63-5251-1211-87-0MnemonicReservedPhysBaseReservedTypeDescriptionReserved, Must be ZeroRange Physical Base AddressReserved, Must be ZeroDefault Memory TypeFigure 7-6.Memory System870TypeR/WR/WR/WMTRRphysBasen Register185AMD64 Technology24593—Rev. 3.13—July 2007MTRRphysMaskn Registers. The fields in these variable-range MTRRs, shown in Figure 7-7, are:••Valid (V)—Bit 11. Indicates that the MTRR pair is valid (enabled) when set to 1. When the valid bitis cleared to 0 the register pair is not used.Range Physical Mask (PhysMask)—Bits 51–12.
The mask value used to specify the memoryrange. Like PhysBase, PhysMask is aligned on a 4-Kbyte physical-address boundary. Bits 11–0 ofPhysMask are assumed to be 0.6352 5132PhysMaskReserved, MBZ(This is an architectural limit. A given implementation may support fewer bits.)3112 11 10PhysMaskBits63-5251-121110-0MnemonicReservedPhysMaskVReservedVDescriptionReserved, Must be ZeroRange Physical MaskMTRR Pair Enable (Valid)Reserved, Must be ZeroFigure 7-7.0Reserved, MBZR/WR/WR/WMTRRphysMaskn RegisterPhysMask and PhysBase are used together to determine whether a target physical-address falls withinthe specified address range. PhysMask is logically ANDed with PhysBase and separately ANDed withthe upper 40 bits of the target physical-address.
If the results of the two operations are identical, thetarget physical-address falls within the specified memory range. The pseudo-code for the operation is:MaskBase = PhysMask AND PhysBaseMaskTarget = PhysMask AND Target_Address[51:12]if MaskBase = MaskTargetthen Target_Address_In_Rangeelse Target_Address_Not_In_RangeVariable Range Size and Alignment.
The size and alignment of variable memory-ranges (MTRRs)and I/O ranges (IORRs) are restricted as follows:••The boundary on which a variable range is aligned must be equal to the range size. For example, amemory range of 16 Mbytes must be aligned on a 16-Mbyte boundary.The range size must be a power of 2 (2n, 52 > n > 11), with a minimum allowable size of 4 Kbytes.For example, 4 Mbytes and 8 Mbytes are allowable memory range sizes, but 6 Mbytes is notallowable.186Memory System24593—Rev. 3.13—July 2007AMD64 TechnologyPhysMask and PhysBase Values. Software can calculate the PhysMask value using the followingprocedure:1. Subtract the memory-range physical base-address from the upper physical-address of the memoryrange.2.
Subtract the value calculated in Step 1 from the physical memory size.3. Truncate the lower 12 bits of the result in Step 2 to create the PhysMask value to be loaded intothe MTRRphysMaskn register. Truncation is performed by right-shifting the value 12 bits.For example, assume a 32-Mbyte memory range is specified within the 52-bit physical address space,starting at address 200_0000h. The upper address of the range is 3FF_FFFFh. Following the processoutlined above yields:1.
3FF_FFFFh–200_0000h = 1FF_FFFFh2. F_FFFF_FFFF_FFFF–1FF_FFFFh = F_FFFF_FE00_0000h3. Right shift (F_FFFF_FE00_0000h) by 12 = FF_FFFF_E000hIn this example, the 40-bit value loaded into the PhysMask field is FF_FFFF_E000h.Software must also truncate the lower 12 bits of the physical base-address before loading it into thePhysBase field. In the example above, the 40-bit PhysBase field is 00_0000_2000h.Default-Range MTRRs. Physical addresses that are not within ranges established by fixed-range andvariable-range MTRRs are set to a default memory-type using the MTRRdefType register.
The formatof this register is shown in Figure 7-8.6332Reserved, MBZ3112 11 10 9Reserved, MBZBits63-1211109-87-0MnemonicReservedEFEReservedTypeDescriptionReserved, Must be ZeroMTRR EnableFixed Range EnableReserved, Must be ZeroDefault Memory TypeFigure 7-8.Memory SystemEFE8Res,MBZ70TypeR/WR/WR/WR/WMTRR defType Register Format187AMD64 Technology24593—Rev. 3.13—July 2007The fields within the MTRRdefType register are read/write. These fields are:•••Type—Bits 7–0.
The default memory-type used to characterize physical-memory space. SeeTable 7-5 on page 182 for the type-field encodings. The extended type-field encodings are notsupported by this register.Fixed-Range Enable (FE)—Bit 10. All fixed-range MTRRs are enabled when FE is set to 1.Clearing FE to 0 disables all fixed-range MTRRs. Setting and clearing FE has no effect on thevariable-range MTRRs. The FE bit has no effect unless the E bit is set to 1 (see below).MTRR Enable (E)—Bit 11. This is the MTRR enable bit. All fixed-range and variable-rangeMTRRs are enabled when E is set to 1.
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