Volume 2 System Programming (794096), страница 51
Текст из файла (страница 51)
Out-of-order reads can occur as aresult of out-of-order instruction execution or speculative execution. The processor can readmemory and perform cache refills out-of-order to allow out-of-order execution to proceed.Speculative reads are allowed. A speculative read occurs when the processor begins executing amemory-read instruction before it knows the instruction will actually complete. For example, theprocessor can predict a branch will occur and begin executing instructions following the predictedbranch before it knows whether the prediction is valid.
When one of the speculative instructionsreads data from memory, the read itself is speculative. Cache refills may also be performedspeculatively.Reads can be reordered ahead of writes. Reads are generally given a higher priority by theprocessor than writes because instruction execution stalls if the read data required by an instructionis not immediately available. Allowing reads ahead of writes usually maximizes softwareperformance.A read cannot be reordered ahead of a prior write if the read is from the same location as the priorwrite. In this case, the read instruction stalls until the write instruction completes execution.
The160Memory System24593—Rev. 3.13—July 2007AMD64 Technologyread instruction requires the result of the write instruction for proper software operation. Forcacheable memory types, the write data can be forwarded to the read instruction before it isactually written to memory.7.1.2 Write OrderingWrites affect program order because they affect the state of software-visible resources. The followingrules govern write ordering:•••••Generally, out-of-order writes are not allowed.
Write instructions executed out of order cannotcommit (write) their result to memory until all previous instructions have completed in programorder. The processor can, however, hold the result of an out-of-order write instruction in a privatebuffer (not visible to software) until that result can be committed to memory.It is possible for writes to write-combining memory types to appear to complete out of order,relative to writes into other memory types. See “Memory Types” on page 168 and “WriteCombining” on page 173 for additional information.Speculative writes are not allowed.
As with out-of-order writes, speculative write instructionscannot commit their result to memory until all previous instructions have completed in programorder. Processors can hold the result in a private buffer (not visible to software) until the result canbe committed.Write buffering is allowed. When a write instruction completes and commits its result, that resultcan be buffered before actually writing the result into a memory location in program order.Although the write buffer itself is not directly accessible by software, the results in the buffer areaccessible during memory accesses to the locations that are buffered.
For cacheable memory types,the write buffer can be read out-of-order and speculatively read, just like memory.Write combining is allowed. In some situations software can relax the write-ordering rules andallow several writes to be combined into fewer writes to memory. When write-combining is used, itis possible for writes to other memory types to proceed ahead of (out-of-order) memorycombining writes, unless the writes are to the same address. Write-combining should be used onlywhen the order of writes does not affect program order (for example, writes to a graphics framebuffer).7.1.3 Read/Write BarriersWhen the order of memory accesses must be strictly enforced, software can use read/write barrierinstructions to force reads and writes to proceed in program order.
Read/write barrier instructions forceall prior reads or writes to complete before subsequent reads or writes are executed. The LFENCE,SFENCE, and MFENCE instructions are provided as dedicated read, write, and read/write barrierinstructions (respectively). Serializing instructions, I/O instructions, and locked instructions can alsobe used as read/write barriers. Barrier instructions are useful for controlling ordering between differingmemory types as well as within one memory type; see section 7.3.1 for details.Table 7-1 on page 169 summarizes the memory-access ordering possible for each memory typesupported by the AMD64 architecture.Memory System161AMD64 Technology7.224593—Rev. 3.13—July 2007Multiprocessor Memory Access OrderingThe term memory ordering refers to the sequence in which memory accesses are performed by thememory system, as observed by all processors or programs.To improve performance of applications, AMD64 processors can speculatively execute instructionsout of program order and temporarily hold out-of-order results.
However, certain rules are followedwith regard to normal cacheable accesses on naturally aligned boundaries to WB memory.From the point of view of a program, in ascending order of priority:•All loads, stores and I/O operations from a single processor appear to occur in program order to thecode running on that processor and all instructions appear to execute in program order.In this context:- Loads do not pass previous loads (loads are not re-ordered). Stores do not pass previous stores(stores are not re-ordered)In the examples below all memory values are initialized to zero.Processor 0Store A ← 1Store B ← 1-Processor 1Load BLoad ALoad A cannot read 0 when Load B reads 1.
(This rule may be violated in the case of loads aspart of a string operation, in which one iteration of the string reads 0 for Load A while anotheriteration reads 1 for Load B.)Stores do not pass loadsProcessor 0Load AStore B ← 1Processor 1Load BStore A ← 1Load A and Load B cannot both read 1.•Stores from a processor appear to be committed to the memory system in program order; however,stores can be delayed arbitrarily by store buffering while the processor continues operation. For thecode example below, both load A in processor 1 and load B in processor 0 can read 1 from the firststore in each processor.
Therefore, stores from a processor may not appear to be sequentiallyconsistent.162Memory System24593—Rev. 3.13—July 2007AMD64 TechnologyProcessor 0Store A ← 1…Store A ← 2…Load B-Processor 1Store B ← 1…Store B ← 2…Load ANon-overlapping Loads may pass stores.Processor 0Store A ← 1Load BProcessor 1Store B ← 1Load AAll combinations of Load A and Load B values are allowed. Where sequential consistency isneeded (for example in Dekker’s algorithm for mutual exclusion), an MFENCE instructionshould be used between the store and the subsequent load, or a locked access, such as LOCKXCHG, should be used for the store.Processor 0Store A ← 1MFENCELoad BProcessor 1Store B ← 1MFENCELoad ALoad A and Load B cannot both read 0.-Stores to different locations in memory observed from two (or more) processors may beinterleaved in different ways for different observers. In the code example,Processor 0Store A ← 1Processor 1Store B ← 1Processor XProcessor YLoad A (1)Load B (0)Load B (1)Load A (0)processor X may see the store A from processor 0 before the store B from processor 1, whileprocessor Y may see the store B from processor 1 before the store A from processor 0.To provide a single point of global visibility, to enable processors X and Y to see the storesfrom processors 0 and 1 in the same order, locked accesses, which atomically load and storeshared data (and provide sequential consistency), must be used for the stores, as follows.Memory System163AMD64 TechnologyProcessor 0LOCK XCHG A, 1•24593—Rev.
3.13—July 2007Processor 1LOCK XCHG B, 1Processor XProcessor YLoad A (1)Load B (0)Load B (1)Load A (0)The illustrated case—in which processor X may see LOCK XCHG A from processor 0 beforeLOCK XCHG B from processor 1, while processor Y may see LOCK XCHG B fromprocessor 1 before LOCK XCHG A from processor 0—is not allowed.Dependent stores between different processors appear to occur in program order, as shown in thecode example below.Processor 0Store A ← 1Processor 1Processor 2Load A (1)Store B ← 1Load B (1)Load A (1)If processor 1 reads a value from A (written by processor 0) before carrying out a store to B, and ifprocessor 2 reads the updated value from B, a subsequent read of A must also be the updated value.A globally consistent ordering is maintained for such causally-related stores.•There can be different points of visibility for a memory operation, including local (within aprocessor), non-local (within a subset of processors) and global (across the system).
Using a databypass, a local load can read the result of a local store in a store buffer, before the store becomesnon-locally visible. Program order is still maintained when using such bypasses.Processor 0Store A ← 1Load r1 ALoad r2 BProcessor 1Store B ← 1Load r3 BLoad r4 ALoad A in processor 0 can read 1 using the data bypass, while Load A in processor 1 can read 0.Similarly, Load B in processor 1 can read 1 while Load B in processor 0 can read 0. Thereforeresult r1 = 1, r2 = 0, r3 = 1 and r4 = 0 is allowed.
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