Volume 2 System Programming (794096), страница 49
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Theinstruction is privileged and causes a #GP to occur if non-privileged software attempts to execute it.The store machine status word (SMSW) instruction stores all 16 status-word bits (CR0[15:0]) into thetarget GPR or memory location. The instruction is not privileged and can be executed by all software.CLTS Instruction. The clear task-switched bit instruction (CLTS) clears CR0.TS to 0. The CR0.TSbit is set to 1 by the processor every time a task switch takes place.
The bit is useful to system softwarein determining when the x87 and multimedia register state should be saved or restored. See “TaskSwitched (TS) Bit” on page 44 for more information on using CR0.TS to manage x87-instructionstate. The CLTS instruction is privileged and causes a #GP to occur if non-privileged software attemptsto execute it.System-Management Instructions151AMD64 Technology24593—Rev.
3.13—July 20076.2.3 Accessing the RFLAGs RegisterThe RFLAGS register contains both application and system bits. This section describes theinstructions used to read and write system bits. Descriptions of instruction effects on application flagscan be found in “Flags Register” in Volume 1 and “Instruction Effects on RFLAGS” in Volume 3.POPF and PUSHF Instructions. The pop and push RFLAGS instructions are used for moving databetween the rFLAGS register and the stack.
They are not system-management instructions, but theirbehavior is mode-dependent.CLI and STI Instructions. The clear interrupt (CLI) and set interrupt (STI) instructions modify onlythe RFLAGS.IF bit or RFLAGS.VIF bit. Clearing rFLAGS.IF to 0 causes the processor to ignoremaskable interrupts. Setting RFLAGS.IF to 1 causes the processor to allow maskable interrupts.See “Virtual Interrupts” on page 245 for more information on the operation of these instructions whenvirtual-8086 mode extensions are enabled (CR4.VME=1).6.2.4 Accessing Debug RegistersThe MOV DRn instructions are used to copy data between the debug registers and the general-purposeregisters.
These instructions are privileged and cause a general-protection exception (#GP) if nonprivileged software attempts to execute them. See “Debug Registers” on page 326 for a detaileddescription of the debug registers.6.2.5 Accessing Model-Specific RegistersRDMSR and WRMSR Instructions. The read/write model-specific register instructions (RDMSRand WRMSR) can be used by privileged software to access the 64-bit MSRs. See “Model-SpecificRegisters (MSRs)” on page 56 for details about the MSRs.RDPMC Instruction. The read performance-monitoring counter instruction, RDPMC, is used to readthe model-specific performance-monitor registers, PerfCTR[3:0].RDTSC Instruction.
The read time-stamp counter instruction, RDTSC, is used to read the model-specific time-stamp counter (TSC) register.RDTSCP Instruction. The read time-stamp counter and processor ID instruction, RDTSCP, is usedto read the model-specific time-stamp counter (TSC) register. as well as the low 32 bits of theTSC_AUX register (MSR C000_0103h).6.3Segment Register and Descriptor Register AccessThe AMD64 architecture supports the legacy instructions that load and store segment registers anddescriptor registers. In some cases the instruction capabilities are expanded to support long mode.152System-Management Instructions24593—Rev.
3.13—July 2007AMD64 Technology6.3.1 Accessing Segment RegistersMOV, POP, and PUSH Instructions. The MOV and POP instructions can be used to load a selectorinto a segment register from a general-purpose register or memory (MOV) or from the stack (POP).Any segment register, except the CS register, can be loaded with the MOV and POP instructions. TheCS register must be loaded with a far-transfer instruction.All segment register selectors can be stored in a general-purpose register or memory using the MOVinstruction or pushed onto the stack using the PUSH instruction.When a selector is loaded into a segment register, the processor automatically loads the correspondingdescriptor-table entry into the hidden portion of the selector register. The hidden portion contains thebase address, limit, and segment attributes.Segment-load and segment-store instructions work normally in 64-bit mode.
The appropriate entry isread from the system descriptor table (GDT or LDT) and is loaded into the hidden portion of thesegment descriptor register. However, the contents of data-segment and stack-segment descriptorregisters are ignored, except in the case of the FS and GS segment-register base fields—see “FS andGS Registers in 64-Bit Mode” on page 70 for more information.The ability to use segment-load instructions allows a 64-bit operating system to set up segmentregisters for a compatibility-mode application before switching to compatibility mode.6.3.2 Accessing Descriptor-Table RegistersLGDT and LIDT Instructions. The load GDTR (LGDT) and load IDTR (LIDT) instructions load apseudo-descriptor from memory into the GDTR or IDTR registers, respectively.LLDT and LTR Instructions.
The load LDTR (LLDT) and load TR (LTR) instructions load a system-segment descriptor from the GDT into the LDTR and TR segment-descriptor registers (hiddenportion), respectively.SGDT and SIDT Instructions. The store GDTR (SGDT) and store IDTR (SIDT) instructions reversethe operation of the LGDT and LIDT instructions. SGDT and SIDT store a pseudo-descriptor from theGDTR or IDTR register into memory.SLDT and STR Instructions. In all modes, the store LDTR (SLDT) and store TR (STR) instructionsstore the LDT or task selector from the visible portion of the LDTR or TR register into a generalpurpose register or memory, respectively. The hidden portion of the LDTR or TR register is not stored.6.4Protection CheckingSeveral instructions are provided to allow software to determine the outcome of a protection checkbefore performing a memory access that could result in a protection violation. By performing thechecks before a memory access, software can avoid violations that result in a general-protectionexception (#GP).System-Management Instructions153AMD64 Technology24593—Rev.
3.13—July 20076.4.1 Checking Access RightsLAR Instruction. The load access-rights (LAR) instruction can be used to determine if access to asegment is allowed, based on privilege checks and type checks. The LAR instruction uses a segmentselector in the source operand to reference a descriptor in the GDT or LDT.
LAR performs a set ofaccess-rights checks and, if successful, loads the segment-descriptor access rights into the destinationregister. Software can further examine the access-rights bits to determine if access into the segment isallowed.6.4.2 Checking Segment LimitsLSL Instruction. The load segment-limit (LSL) instruction uses a segment-selector in the sourceoperand to reference a descriptor in the GDT or LDT. LSL performs a set of preliminary access-rightschecks and, if successful, loads the segment-descriptor limit field into the destination register.Software can use the limit value in comparisons with pointer offsets to prevent segment limitviolations.6.4.3 Checking Read/Write RightsVERR and VERW Instructions.
The verify read-rights (VERR) and verify write-rights (VERW) canbe used to determine if a target code or data segment (not a system segment) can be read or writtenfrom the current privilege level (CPL). The source operand for these instructions is a pointer to thesegment selector to be tested. If the tested segment (code or data) is readable from the current CPL, theVERR instruction sets RFLAGS.ZF to 1; otherwise, it is cleared to zero. Likewise, if the tested datasegment is writable, the VERW instruction sets the RFLAGS.ZF to 1.
A code segment cannot be testedfor writability.6.4.4 Adjusting Access RightsARPL Instruction. The adjust RPL-field (ARPL) instruction can be used by system software toprevent access into privileged-data segments by lower-privileged software. This can happen if anapplication passes a selector to system software and the selector RPL is less than (has greater privilegethan) the calling-application CPL. To prevent this surrogate access, system software executes ARPLwith the following operands:••The destination operand is the data-segment selector passed to system software by the application.The source operand is the application code-segment selector (available on the system-softwarestack as a result of the CALL into system software by the application).ARPL is not supported in 64-bit mode.6.5Processor HaltThe processor halt instruction (HLT) halts instruction execution, leaving the processor in the halt state.No registers or machine state are modified as a result of executing the HLT instruction.
The processorremains in the halt state until one of the following occurs:154System-Management Instructions24593—Rev. 3.13—July 2007•••••AMD64 TechnologyA non-maskable interrupt (NMI).An enabled, maskable interrupt (INTR).Processor reset (RESET).Processor initialization (INIT).System-management interrupt (SMI).6.6Cache and TLB ManagementCache-management instructions are used by system software to maintain coherency within thememory hierarchy. Memory coherency and caches are discussed in Chapter 7, “Memory System.”Similarly, TLB-management instructions are used to maintain coherency between page translationscached in the TLB and the translation tables maintained by system software in memory. See“Translation-Lookaside Buffer (TLB)” on page 139 for more information.6.6.1 Cache ManagementWBINVD Instruction. The writeback and invalidate (WBINVD) instruction is used to write allmodified cache lines to memory so that memory contains the most recent copy of data.
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