Volume 2 System Programming (794096), страница 45
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The size of the field depends on the mode:••In normal (non-PAE) paging (CR4.PAE=0), this field specifies a 32-bit base address for a physicalpage.In PAE paging (CR4.PAE=1), this field specifies a 52-bit base address for a physical page.Physical pages can be 4 Kbytes, 2 Mbytes, 4 Mbytes, or 1-Gbyte and they are always aligned on anaddress boundary corresponding to the physical-page length. For example, a 2-Mbyte physical page isalways aligned on a 2-Mbyte address boundary. Because of this alignment, the low-order address bitsare assumed to be 0, as follows:••••4-Kbyte pages, bits 11–0 are assumed 0.2-Mbyte pages, bits 20–0 are assumed 0.4-Mbyte pages, bits 21–0 are assumed 0.1-Gbyte pages, bits 29–0 are assumed 0.Present (P) Bit. Bit 0. This bit indicates whether the page-translation table or physical page is loadedin physical memory.
When the P bit is cleared to 0, the table or physical page is not loaded in physicalmemory. When the P bit is set to 1, the table or physical page is loaded in physical memory.Software clears this bit to 0 to indicate a page table or physical page is not loaded in physical memory.A page-fault exception (#PF) occurs if an attempt is made to access a table or page when the P bit is 0.System software is responsible for loading the missing table or page into memory and setting the P bitto 1.136Page Translation and Protection24593—Rev.
3.13—July 2007AMD64 TechnologyWhen the P bit is 0, indicating a not-present page, all remaining bits in the page data-structure entry areavailable to software.Entries with P cleared to 0 are never cached in TLB nor will the processor set the Accessed or Dirty bitfor the table entry.Read/Write (R/W) Bit. Bit 1. This bit controls read/write access to all physical pages mapped by thetable entry. For example, a page-map level-4 R/W bit controls read/write access to all 128M(512 × 512 × 512) physical pages it maps through the lower-level translation tables. When the R/W bitis cleared to 0, access is restricted to read-only.
When the R/W bit is set to 1, both read and write accessis allowed. See “Page-Protection Checks” on page 141 for a description of the paging read/writeprotection mechanism.User/Supervisor (U/S) Bit. Bit 2. This bit controls user (CPL 3) access to all physical pages mappedby the table entry. For example, a page-map level-4 U/S bit controls the access allowed to all 128M(512 × 512 × 512) physical pages it maps through the lower-level translation tables. When the U/S bitis cleared to 0, access is restricted to supervisor level (CPL 0, 1, 2). When the U/S bit is set to 1, bothuser and supervisor access is allowed. See “Page-Protection Checks” on page 141 for a description ofthe paging user/supervisor protection mechanism.Page-Level Writethrough (PWT) Bit. Bit 3.
This bit indicates whether the page-translation table orphysical page to which this entry points has a writeback or writethrough caching policy. When thePWT bit is cleared to 0, the table or physical page has a writeback caching policy. When the PWT bit isset to 1, the table or physical page has a writethrough caching policy. See “Memory Caches” onpage 174 for additional information on caching.Page-Level Cache Disable (PCD) Bit. Bit 4. This bit indicates whether the page-translation table orphysical page to which this entry points is cacheable.
When the PCD bit is cleared to 0, the table orphysical page is cacheable. When the PCD bit is set to 1, the table or physical page is not cacheable.See “Memory Caches” on page 174 for additional information on caching.Accessed (A) Bit. Bit 5. This bit indicates whether the page-translation table or physical page towhich this entry points has been accessed. The A bit is set to 1 by the processor the first time the tableor physical page is either read from or written to.
The A bit is never cleared by the processor. Instead,software must clear this bit to 0 when it needs to track the frequency of table or physical-page accesses.Dirty (D) Bit. Bit 6. This bit is only present in the lowest level of the page-translation hierarchy. Itindicates whether the page-translation table or physical page to which this entry points has beenwritten. The D bit is set to 1 by the processor the first time there is a write to the physical page. The Dbit is never cleared by the processor.
Instead, software must clear this bit to 0 when it needs to track thefrequency of physical-page writes.Page Size (PS) Bit. Bit 7. This bit is present in page-directory entries and long-mode page-directory-pointer entries. When the PS bit is set in the page-directory-pointer entry (PDPE) or page-directoryentry (PDE), that entry is the lowest level of the page-translation hierarchy. When the PS bit is clearedPage Translation and Protection137AMD64 Technology24593—Rev.
3.13—July 2007to 0 in all levels, the lowest level of the page-translation hierarchy is the page-table entry (PTE), andthe physical-page size is 4 Kbytes. The physical-page size is determined as follows:•••If EFER.LMA=1 and PDPE.PS=1, the physical-page size is 1 Gbyte.If CR4.PAE=0 and PDE.PSE=1, the physical-page size is 4 Mbytes.If CR4.PAE=1 and PDE.PSE=1, the physical-page size is 2 Mbytes.See Table 5-1 on page 118 for a description of the relationship between the PS bit, PAE, physical-pagesizes, and page-translation hierarchy.Global Page (G) Bit. Bit 8. This bit is only present in the lowest level of the page-translationhierarchy.
It indicates the physical page is a global page. The TLB entry for a global page (G=1) is notinvalidated when CR3 is loaded either explicitly by a MOV CRn instruction or implicitly during a taskswitch. Use of the G bit requires the page-global enable bit in CR4 to be set to 1 (CR4.PGE=1). See“Global Pages” on page 140 for more information on the global-page mechanism.Available to Software (AVL) Bit. These bits are not interpreted by the processor and are available foruse by system software.Page-Attribute Table (PAT) Bit.
This bit is only present in the lowest level of the page-translationhierarchy, as follows:••If the lowest level is a PTE (PDE.PS=0), PAT occupies bit 7.If the lowest level is a PDE (PDE.PS=1) or PDPE (PDPE.PS=1), PAT occupies bit 12.The PAT bit is the high-order bit of a 3-bit index into the PAT register (Figure 7-10 on page 191). Theother two bits involved in forming the index are the PCD and PWT bits. Not all processors support thePAT bit by implementing the PAT registers.
See “Page-Attribute Table Mechanism” on page 191 for adescription of the PAT mechanism and how it is used.No Execute (NX) Bit. Bit 63. This bit is present in the translation-table entries defined for PAEpaging, with the exception that the legacy-mode PDPE does not contain this bit. This bit is notsupported by non-PAE paging.The NX bit can only be set when the no-execute page-protection feature is enabled by settingEFER.NXE to 1 (see “Extended Feature Enable Register (EFER)” on page 54). If EFER.NXE=0, theNX bit is treated as reserved.
In this case, a page-fault exception (#PF) occurs if the NX bit is notcleared to 0.This bit controls the ability to execute code from all physical pages mapped by the table entry. Forexample, a page-map level-4 NX bit controls the ability to execute code from all 128M(512 × 512 × 512) physical pages it maps through the lower-level translation tables.
When the NX bitis cleared to 0, code can be executed from the mapped physical pages. When the NX bit is set to 1, codecannot be executed from the mapped physical pages. See “No Execute (NX) Bit” on page 141 for adescription of the no-execute page-protection mechanism.138Page Translation and Protection24593—Rev. 3.13—July 2007AMD64 TechnologyReserved Bits.
Software should clear all reserved bits to 0. If the processor is in long mode, or ifpage-size and physical-address extensions are enabled in legacy mode, a page-fault exception (#PF)occurs if reserved bits are not cleared to 0.5.4.2 Notes on Access and Dirty bitsThe processor never sets the Accessed bit or the Dirty bit for a not present page (P = 0). The ordering ofAccessed and Dirty bit updates with respect to surrounding loads and stores is discussed below.Accessed bit.
The Accessed bit can be set for instructions that are speculatively executed by theprocessor.For example, the Accessed bit may be set by instructions in a mispredicted branch path even thoughthose instructions are never retired. Thus, software must not assume that the TLB entry has not beencached in the TLB, just because no instruction that accessed the page was successfully retired.Nevertheless, a table entry is never cached in the TLB without its Accessed bit being set at the sametime.The processor does not order Accessed bit updates with respect to loads done by other instructions.Dirty bit. The Dirty bit is not updated speculatively. For instructions with multiple writes, the D bitmay be set for any writes completed up to the point of a fault.
In rare cases, the Dirty bit may be seteven if a write was not actually performed, including MASKMOVQ with a mask of zero and certainx87 floating point instructions that cause an exception. Thus software can not assume that the page hasactually been written even where PTE.D is set to 1.If PTE.D is cleared to 0, software can rely on the fact that the page has not been written.Dirty bit updates are ordered with respect to other loads and stores. However, to ensure compatibilitywith future processors, a serializing operation should be inserted before reading the D bit.5.5Translation-Lookaside Buffer (TLB)When paging is enabled, every memory access has its virtual address automatically translated into aphysical address using the page-translation hierarchy.
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