Volume 2 System Programming (794096), страница 43
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With PAE paging, 4-Kbyte physical-page translation is performed bydividing the 32-bit virtual address into four fields, each of the upper three fields is used as an index intoa 3-level page-translation hierarchy. The virtual-address fields are described as follows and are shownin Figure 5-9:••••Bits 31–30 index into a 4-entry page-directory-pointer table.Bits 29–21 index into the 512-entry page-directory table.Bits 20–12 index into the 512-entry page table.Bits 11–0 provide the byte offset into the physical page.Virtual Address3130 29Page-DirectoryPointer Offset21 20Page-DirectoryOffset212 11Page-TableOffset9Page Offset9PageDirectoryTablePageDirectoryPointerTable0124 KbytePhysicalPagePageTablePTE52*52*PDPEPhysicalAddress52*PDE315Page-Directory-Pointer Base*This is an architectural limit.
A given processorimplementation may support fewer bits.CR3Figure 5-9. 4-Kbyte PAE Page Translation—Legacy ModePage Translation and Protection125AMD64 Technology24593—Rev. 3.13—July 2007Figures 5-10 through 5-12 show the legacy-mode 4-Kbyte translation-table formats:••Figure 5-10 shows the PDPE (page-directory-pointer entry) format.Figure 5-11 shows the PDE (page-directory entry) format.•Figure 5-12 shows the PTE (page-table entry) format.The fields within these table entries are described in “Page-Translation-Table Entry Fields” onpage 135.Figure 5-11 shows the PDE.PS bit cleared to 0 (bit 7), specifying a 4-Kbyte physical-page translation.6352 5132Page-Directory Base Address(This is an architectural limit. A given implementation may support fewer bits.)Reserved, MBZ3112 11Page-Directory Base AddressFigure 5-10.63 62NX985Reserved,MBZAVL4 3 2 1P PC W MBZD T0P4-Kbyte PDPE—PAE Paging Legacy-Mode52 5132Page-Table Base Address(This is an architectural limit.
A given implementation may support fewer bits.)Reserved, MBZ3112 11Page-Table Base Address9AVL8IGN706 5 4 3 2 1 0IP P U RG A C W / / PND T S WFigure 5-11. 4-Kbyte PDE—PAE Paging Legacy-Mode63 62NX52 51Reserved, MBZ32Physical-Page Base Address(This is an architectural limit. A given implementation may support fewer bits.)3112 11Physical-Page Base Address9AVL87 6 5 4 3 2 1 0PP P U RG A D A C W / / PTD T S WFigure 5-12. 4-Kbyte PTE—PAE Paging Legacy-Mode2-Mbyte Page Translation. 2-Mbyte page translation is performed by dividing the 32-bit virtualaddress into three fields. Each field is used as an index into a 2-level page-translation hierarchy. Thevirtual-address fields are described as follows and are shown in Figure 5-13 on page 127:126Page Translation and Protection24593—Rev. 3.13—July 2007•••AMD64 TechnologyBits 31–30 index into the 4-entry page-directory-pointer table.Bits 29–21 index into the 512-entry page-directory table.Bits 20–0 provide the byte offset into the physical page.Virtual Address3130 2921 200Page-DirectoryOffsetPage-DirectoryPointer Offset2Page Offset9212 MbytePhysicalPagePageDirectoryTablePageDirectoryPointerTable52*PDPEPhysicalAddress52*PDE315Page-Directory-Pointer Base RegisterFigure 5-13.*This is an architectural limit.
A given processorimplementation may support fewer bits.CR32-Mbyte PAE Page Translation—Legacy ModeFigure 5-14 shows the format of the PDPE (page-directory-pointer entry) and Figure 5-15 on page 128shows the format of the PDE (page-directory entry). PTEs are not used in 2-Mbyte page translations.Figure 5-15 on page 128 shows the PDE.PS bit set to 1 (bit 7), specifying a 2-Mbyte physical-pagetranslation.6352 51Reserved, MBZ32Page-Directory Base Address(This is an architectural limit. A given implementation may support fewer bits.)3112 11Page-Directory Base Address9AVL85Reserved,MBZ4 3 2 1P PC W MBZD T0PFigure 5-14.
2-Mbyte PDPE—PAE Paging Legacy-ModePage Translation and Protection127AMD64 Technology63 62NX24593—Rev. 3.13—July 200752 51Physical-Page Base Address(This is an architectural limit. A given implementation may support fewer bits.)Reserved, MBZ313221 20Physical-Page Base AddressReserved, MBZ13 12 119PAAVLT87G1654 3 2 1 0P P U RD A C W / / PD T S WFigure 5-15. 2-Mbyte PDE—PAE Paging Legacy-Mode5.3Long-Mode Page TranslationLong-mode page translation requires the use of physical-address extensions (PAE). Before activatinglong mode, PAE must be enabled by setting CR4.PAE to 1.
Activating long mode before enabling PAEcauses a general-protection exception (#GP) to occur.The PAE-paging data structures support mapping of 64-bit virtual addresses into 52-bit physicaladdresses. PAE expands the size of legacy page-directory entries (PDEs) and page-table entries (PTEs)from 32 bits to 64 bits, allowing physical-address sizes of greater than 32 bits.The AMD64 architecture enhances the page-directory-pointer entry (PDPE) by defining previouslyreserved bits for access and protection control.
A new translation table is added to PAE paging, calledthe page-map level-4 (PML4). The PML4 table precedes the PDP table in the page-translationhierarchy.Because PAE is always enabled in long mode, the PS bit in the page directory entry (PDE.PS) selectsbetween 4-Kbyte and 2-Mbyte page sizes, and the CR4.PSE bit is ignored.
When 1-Gbyte pages aresupported, the PDPE. PS bit selects the 1-Gbyte page size.5.3.1 Canonical Address FormThe AMD64 architecture requires implementations supporting fewer than the full 64-bit virtualaddress to ensure that those addresses are in canonical form. An address is in canonical form if theaddress bits from the most-significant implemented bit up to bit 63 are all ones or all zeros.
If theaddresses of all bytes in a virtual-memory reference are not in canonical form, the processor generatesa general-protection exception (#GP) or a stack fault (#SS) as appropriate.5.3.2 CR3In long mode, the CR3 register is used to point to the PML4 base address. CR3 is expanded to 64 bitsin long mode, allowing the PML4 table to be located anywhere in the 52-bit physical-address space.Figure 5-16 on page 129 shows the long-mode CR3 format.128Page Translation and Protection24593—Rev. 3.13—July 200763AMD64 Technology52 51Reserved, MBZ32Page-Map Level-4 Table Base Address(This is an architectural limit. A given implementation may support fewer bits.)3112 11Page-Map Level-4 Table Base Address5Reserved4 3 20P PC W ReservedD TFigure 5-16. Control Register 3 (CR3)—Long ModeThe CR3 register fields for long mode are:Table Base Address Field.
Bits 51–12. This 40-bit field points to the PML4 base address. ThePML4 table is aligned on a 4-Kbyte boundary with the low-order 12 address bits (11–0) assumed to be0. This yields a total base-address size of 52 bits. System software running on processorimplementations supporting less than the full 52-bit physical-address space must clear theunimplemented upper base-address bits to 0.Page-Level Writethrough (PWT) Bit.
Bit 3. Page-level writethrough indicates whether the highest-level page-translation table has a writeback or writethrough caching policy. When PWT=0, the tablehas a writeback caching policy. When PWT=1, the table has a writethrough caching policy.Page-Level Cache Disable (PCD) Bit.
Bit 4. Page-level cache disable indicates whether the highest-level page-translation table is cacheable. When PCD=0, the table is cacheable. When PCD=1, the tableis not cacheable.Reserved Bits. Reserved fields should be cleared to 0 by software when writing CR3.5.3.3 4-Kbyte Page TranslationIn long mode, 4-Kbyte physical-page translation is performed by dividing the virtual address into sixfields. Four of the fields are used as indices into the level page-translation hierarchy. The virtualaddress fields are described as follows, and are shown in Figure 5-17 on page 130:• Bits 63–48 are a sign extension of bit 47, as required for canonical-address forms.• Bits 47–39 index into the 512-entry page-map level-4 table.• Bits 38–30 index into the 512-entry page-directory pointer table.• Bits 29–21 index into the 512-entry page-directory table.• Bits 20–12 index into the 512-entry page table.• Bits 11–0 provide the byte offset into the physical page.Note: The sizes of the sign extension and the PML4 fields depend on the number of virtual addressbits supported by the implementation.Page Translation and Protection129AMD64 Technology24593—Rev.
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