Volume 2 System Programming (794096), страница 46
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Translation-lookaside buffers (TLBs), alsoknown as page-translation caches, nearly eliminate the performance penalty associated with pagetranslation. TLBs are special on-chip caches that hold the most-recently used virtual-to-physicaladdress translations. Each memory reference (instruction and data) is checked by the TLB.
If thetranslation is present in the TLB, it is immediately provided to the processor, thus avoiding externalmemory references for accessing page tables.TLBs take advantage of the principle of locality. That is, if a memory address is referenced, it is likelythat nearby memory addresses will be referenced in the near future. In the context of paging, theproximity of memory addresses required for locality can be broad—it is equal to the page size.
Thus, itis possible for a large number of addresses to be translated by a small number of page translations. Thishigh degree of locality means that almost all translations are performed using the on-chip TLBs.Page Translation and Protection139AMD64 Technology24593—Rev. 3.13—July 2007System software is responsible for managing the TLBs when updates are made to the linear-tophysical mapping of addresses.
A change to any paging data-structure entry is not automaticallyreflected in the TLB, and hardware snooping of TLBs during memory-reference cycles is notperformed. Software must invalidate the TLB entry of a modified translation-table entry so that thechange is reflected in subsequent address translations. TLB invalidation is described in “TLBManagement” on page 140. Only privileged software running at CPL=0 can manage the TLBs.5.5.1 Global PagesThe processor invalidates the TLB whenever CR3 is loaded either explicitly or implicitly. After theTLB is invalidated, subsequent address references can consume many clock cycles until theirtranslations are cached as new entries in the TLB.
Invalidation of TLB entries for frequently-used orcritical pages can be avoided by specifying the translations for those pages as global. TLB entries forglobal pages are not invalidated as a result of a CR3 load. Global pages are invalidated using theINVLPG instruction.Global-page extensions are controlled by setting and clearing the PGE bit in CR4 (bit 7). WhenCR4.PGE is set to 1, global-page extensions are enabled. When CR4.PGE is cleared to 0, global-pageextensions are disabled. When CR4.PGE=1, setting the global (G) bit in the translation-table entrymarks the page as global.The INVLPG instruction ignores the G bit and can be used to invalidate individual global-page entriesin the TLB. To invalidate all entries, including global-page entries, disable global-page extensions(CR4.PGE=0).5.5.2 TLB ManagementGenerally, unless system software modifies the linear-to-physical address mapping, the processormanages the TLB transparently to software.
This includes allocating entries and replacing old entrieswith new entries. Software changes made to paging-data structures are not automatically reflected inthe TLB. In these situations, it is necessary for software to invalidate TLB entries so that these changesare immediately propagated to the page-translation mechanism.TLB entries can be explicitly invalidated using operations intended for that purpose or implicitlyinvalidated as a result of another operation. TLB invalidation has no effect on the associated pagetranslation tables in memory.Explicit Invalidations. Three mechanisms are provided to explicitly invalidate the TLB:••The invalidate TLB entry instruction (INVLPG) can be used to invalidate specific entries withinthe TLB. This instruction invalidates a page, regardless of whether it is marked as global or not.The Invalidate TLB entry in a Specified ASID (INVLPGA) operates similarly, but operates on thespecified ASID.
See “Invalidate Page, Alternate ASID” on page 388.Updates to the CR3 register cause the entire TLB to be invalidated except for global pages. TheCR3 register can be updated with the MOV CR3 instruction. CR3 is also updated during a taskswitch, with the updated CR3 value read from the TSS of the new task.140Page Translation and Protection24593—Rev. 3.13—July 2007•AMD64 TechnologyThe TLB_CONTROL field of a VMCB can request specific flushes of the TLB to occur when theVMRUN instruction is executed on that VMCB.
See “TLB Flush” on page 388.Implicit Invalidations. The following operations cause the entire TLB to be invalidated, includingglobal pages:••••••••Modifying the CR0.PG bit (paging enable).Modifying the CR4.PAE bit (physical-address extensions), the CR4.PSE bit (page-sizeextensions), or the CR4.PGE bit (page-global enable).Entering SMM as a result of an SMI interrupt.Executing the RSM instruction to return from SMM.Updating a memory-type range register (MTRR) with the WRMSR instruction.External initialization of the processor.External masking of the A20 address bit (asserting the A20M# input signal).Writes to certain model-specific registers with the WRMSR instruction; see the BIOS and KernelDeveloper's Guide for the processor implementation for more information5.6Page-Protection ChecksTwo forms of page-level memory protection are provided by the legacy architecture.
The first form ofprotection prevents non-privileged (user) code and data from accessing privileged (supervisor) codeand data. The second form of protection prevents writes into read-only address spaces. The AMD64architecture introduces a third form of protection that prevents software from attempting to executedata pages as instructions. All of these forms of protection are available at all levels of the pagetranslation hierarchy.The processor checks a page for execute permission only when the page translation is loaded into theinstruction TLB as a result of a page-table walk. The remaining protection checks are performed whena virtual address is translated into a physical address. For those checks, the processor examines thepage-level memory-protection bits in the translation tables to determine if the access is allowed.
Thebits involved in these checks are:••User/Supervisor (U/S)—The U/S bit is introduced in “User/Supervisor (U/S) Bit” on page 137.Read/Write (R/W)—The R/W bit is introduced in “Read/Write (R/W) Bit” on page 137.•Write-Protect Enable (CR0.WP)—The CR0.WP bit is introduced in “Write Protect (WP) Bit” onpage 44.5.6.1 No Execute (NX) BitThe NX bit in the page-translation tables specifies whether instructions can be executed from the page.This bit is not checked during every instruction fetch.
Instead, the NX bits in the page-translation-tableentries are checked by the processor when the instruction TLB is loaded with a page translation. Theprocessor attempts to load the translation into the instruction TLB when an instruction fetch misses thePage Translation and Protection141AMD64 Technology24593—Rev. 3.13—July 2007TLB. If a set NX bit is detected (indicating the page is not executable), a page-fault exception (#PF)occurs.The no-execute protection check applies to all privilege levels.
It does not distinguish betweensupervisor and user-level accesses.The no-execute protection feature is supported only in PAE-paging mode. It is enabled by setting theNXE bit in the EFER register to 1 (see “Extended Feature Enable Register (EFER)” on page 54).Before setting this bit, system software must verify the processor supports the NX feature by checkingthe CPUID extended-feature flags (see the AMD CPUID Specification, order# 25481).5.6.2 User/Supervisor (U/S) BitThe U/S bit in the page-translation tables determines the privilege level required to access the page.Conceptually, user (non-privileged) pages correspond to a current privilege-level (CPL) of 3, or leastprivileged.
Supervisor (privileged) pages correspond to a CPL of 0, 1, or 2, all of which are jointlyregarded as most-privileged.When the processor is running at a CPL of 0, 1, or 2, it can access both user and supervisor pages.However, when the processor is running at a CPL of 3, it can only access user pages. If an attempt ismade to access a supervisor page while the processor is running at CPL=3, a page-fault exception(#PF) occurs.See “Segment-Protection Overview” on page 93 for more information on the protection-ring conceptand CPL.5.6.3 Read/Write (R/W) BitThe R/W bit in the page-translation tables specifies the access type allowed for the page. If R/W=1, thepage is read/write.
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