Volume 2 System Programming (794096), страница 41
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Mapping physical pages in this manner allows them to be shared bymultiple processes and applications. The physical pages can be configured by the page tables to allowread-only access. This prevents applications from altering the pages and ensures their integrity for useby all applications.Shared mapping is typically used to allow access of shared-library routines by multiple applications. Aread-only copy of the library routine is mapped to each application virtual-address space, but only asingle copy of the library routine is present in physical memory.
This capability also allows a copy ofthe operating-system kernel and various device drivers to reside within the application address space.Applications are provided with efficient access to system services without requiring costly addressspace switches.The system-software portion of the address space necessarily includes system-only data areas thatmust be protected from accesses by applications.
System software uses the page tables to protect thismemory by designating the pages as supervisor pages. Such pages are only accessible by systemsoftware.Finally, system software can use the paging mechanism to map multiple, large virtual-address spacesinto a much smaller amount of physical memory. Each application can use the entire 32-bit or 64-bitvirtual-address space. System software actively maps the most-frequently-used virtual-memory pagesinto the available pool of physical-memory pages.
The least-frequently-used virtual-memory pages areswapped out to the hard drive. This process is known as demand-paged virtual memory.5.1Page Translation OverviewThe x86 architecture provides support for translating 32-bit virtual addresses into 32-bit physicaladdresses (larger physical addresses, such as 36-bit or 40-bit addresses, are supported as a specialmode). The AMD64 architecture enhances this support to allow translation of 64-bit virtual addressesinto 52-bit physical addresses, although processor implementations can support smaller virtualaddress and physical-address spaces.Page Translation and Protection115AMD64 Technology24593—Rev. 3.13—July 2007Virtual addresses are translated to physical addresses through hierarchical translation tables createdand managed by system software.
Each table contains a set of entries that point to the next-lower tablein the translation hierarchy. A single table at one level of the hierarchy can have hundreds of entries,each of which points to a unique table at the next-lower hierarchical level.
Each lower-level table canin turn have hundreds of entries pointing to tables further down the hierarchy. The lowest-level table inthe hierarchy points to the translated physical page.Figure 5-1 on page 117 shows an overview of the page-translation hierarchy used in long mode.Legacy mode paging uses a subset of this translation hierarchy (the page-map level-4 table does notexist in legacy mode and the PDP table may or may not be used, depending on which paging mode isenabled).
As this figure shows, a virtual address is divided into fields, each of which is used as an offsetinto a translation table. The complete translation chain is made up of all table entries referenced by thevirtual-address fields. The lowest-order virtual-address bits are used as the byte offset into the physicalpage.116Page Translation and Protection24593—Rev. 3.13—July 2007AMD64 Technology64-Bit Virtual Address63SignExtensionPage MapLevel-4 OffsetPage DirectoryPointer OffsetPage DirectoryOffset0Page TableOffsetPhysical PageOffsetPDPEPTEPML4EPDEPhysicalAddressPage MapLevel 4TablePage Directory PointerTablePage Map Base RegisterPage DirectoryTablePageTablePhysical PageFrameCR3513-200.epsFigure 5-1.Virtual to Physical Address Translation—Long ModeLegacy page translation offers a variety of alternatives in translating virtual addresses to physicaladdresses.
Four physical-page sizes of 4 Kbytes, 2 Mbytes and 4 Mbytes are available. VirtualPage Translation and Protection117AMD64 Technology24593—Rev. 3.13—July 2007addresses are 32 bits long, and physical addresses up to the supported physical-address size can beused. The AMD64 architecture enhances the legacy translation support by allowing virtual addressesof up to 64 bits long to be translated into physical addresses of up to 52 bits long.Currently, the AMD64 architecture defines a mechanism for translating 48-bit virtual addresses to 52bit physical addresses.
The mechanism used to translate a full 64-bit virtual address is reserved andwill be described in a future AMD64 architectural specification.5.1.1 Page-Translation OptionsThe form of page-translation support available to software depends on which paging features areenabled. Four controls are available for selecting the various paging alternatives:••••Page-Translation Enable (CR0.PG)Physical-Address Extensions (CR4.PAE)Page-Size Extensions (CR4.PSE)Long-Mode Active (EFER.LMA)Not all paging alternatives are available in all modes. Table 5-1 summarizes the paging supportavailable in each mode.Table 5-1. Supported Paging Alternatives (CR0.PG=1)ModeLongModePhysicalAddressExtensions(CR4.PAE)Page-SizeExtensions(CR4.PSE)64-BitModeCompatibilityModeEnabled–PageDirectoryPointerOffsetPDPE.PS=0PDPE.PS=1Enabled–DisabledLegacy ModeDisabledEnabledPDPE.PS=0PageDirectoryPage SizeResulting Maximum MaximumPhysicalVirtualPhysicalPage Size Address AddressPDE.PS=04 KbytePDE.PS=12 Mbyte–1 GbytePDE.PS=04 Kbyte52-bitPDE.PS=12 Mbyte52-bit–4 KbytePDE.PS=04 Kbyte32-bitPDE.PS=14 Mbyte40-bit64-bit32-bit52-bit32-bit5.1.2 Page-Translation Enable (PG) BitPage translation is controlled by the PG bit in CR0 (bit 31).
When CR0.PG is set to 1, page translationis enabled. When CR0.PG is cleared to 0, page translation is disabled.The AMD64 architecture uses CR0.PG to activate and deactivate long mode when long mode isenabled. See “Enabling and Activating Long Mode” on page 356 for more information.118Page Translation and Protection24593—Rev. 3.13—July 2007AMD64 Technology5.1.3 Physical-Address Extensions (PAE) BitPhysical-address extensions are controlled by the PAE bit in CR4 (bit 5). When CR4.PAE is set to 1,physical-address extensions are enabled. When CR4.PAE is cleared to 0, physical-address extensionsare disabled.Setting CR4.PAE=1 enables virtual addresses to be translated into physical addresses up to 52 bitslong.
This is accomplished by doubling the size of paging data-structure entries from 32 bits to 64 bitsto accommodate the larger physical base-addresses for physical-pages.PAE must be enabled before activating long mode. See “Enabling and Activating Long Mode” onpage 356.5.1.4 Page-Size Extensions (PSE) BitPage-size extensions are controlled by the PSE bit in CR4 (bit 4). Setting CR4.PSE to 1 allowsoperating-system software to use 4-Mbyte physical pages in the translation process. The 4-Mbytephysical pages can be mixed with standard 4-Kbyte physical pages or replace them entirely.
Theselection of physical-page size is made on a page-directory-entry basis. See “Page Size (PS) Bit” onpage 137 for more information on physical-page size selection. When CR4.PSE is cleared to 0, pagesize extensions are disabled.The choice of 2 Mbyte or 4 Mbyte as the large physical-page size depends on the value of CR4.PSEand CR4.PAE, as follows:•••If physical-address extensions are enabled (CR4.PAE=1), the large physical-page size is 2 Mbytes,regardless of the value of CR4.PSE.If physical-address extensions are disabled (CR4.PAE=0) and CR4.PSE=1, the large physicalpage size is 4 Mbytes.If both CR4.PAE=0 and CR4.PSE=0, the only available page size is 4 Kbytes.The value of CR4.PSE is ignored when long mode is active. This is because physical-addressextensions must be enabled in long mode, and the only available page sizes are 4 Kbytes and 2 Mbytes.In legacy mode, physical addresses up to 40 bits long can be translated from 32-bit virtual addressesusing 32-bit paging data-structure entries when 4-Mbyte physical-page sizes are selected.
In thisspecial case, CR4.PSE=1 and CR4.PAE=0. See “4-Mbyte Page Translation” on page 123 for adescription of the 4-Mbyte PDE that supports 40-bit physical-address translation. The 40-bit physicaladdress capability is an AMD64 architecture enhancement over the similar capability available in thelegacy x86 architecture.5.1.5 Page-Directory Page Size (PS) BitThe page directory offset entry (PDE) and page directory pointer offset entry (PDPE) are datastructures used in page translation (see Figure 5-1 on page 117). The page-size (PS) bit in the PDE (bit7, referred to as PDE.PS) selects between standard 4-Kbyte physical-page sizes and larger (2-Mbyte orPage Translation and Protection119AMD64 Technology24593—Rev.
3.13—July 20074-Mbyte) physical-page sizes. The page-size (also PS) bit in the PDPE (bit 7, referred to as PDPE.PS)selects between 2-Mbyte and 1-Gbyte physical-page sizes in long mode.When PDE.PS is set to 1, large physical pages are used, and the PDE becomes the lowest level of thetranslation hierarchy. The size of the large page is determined by the values of CR4.PAE andCR4.PSE, as shown in Figure 5-1 on page 118.
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