Volume 2 System Programming (794096), страница 42
Текст из файла (страница 42)
When PDE.PS is cleared to 0, standard 4-Kbytephysical pages are used, and the PTE is the lowest level of the translation hierarchy.When PDPE.PS is set to 1, 1-Gbyte physical pages are used, and the PDPE becomes the lowest level ofthe translation hierarchy. Neither the PDE nor PTE are used for 1-Gbyte paging.5.2Legacy-Mode Page TranslationLegacy mode supports two forms of translation:••Normal (non-PAE) Paging—This is used when physical-address extensions are disabled(CR4.PAE=0). Entries in the page translation table are 32 bits and are used to translate 32-bitvirtual addresses into physical addresses as large as 40 bits.PAE Paging—This is used when physical-address extensions are enabled (CR4.PAE=1).
Entries inthe page translation table are 64 bits and are used to translate 32-bit virtual addresses into physicaladdresses as large as 52 bits.Legacy paging uses up to three levels of page-translation tables, depending on the paging form usedand the physical-page size. Entries within each table are selected using virtual-address bit fields. Thelegacy page-translation tables are:•••Page Table—Each page-table entry (PTE) points to a physical page.
If 4-Kbyte pages are used, thepage table is the lowest level of the page-translation hierarchy. PTEs are not used when translating2-Mbyte or 4-Mbyte pages.Page Directory—If 4-Kbyte pages are used, each page-directory entry (PDE) points to a pagetable. If 2-Mbyte or 4-Mbyte pages are used, a PDE is the lowest level of the page-translationhierarchy and points to a physical page. In non-PAE paging, the page directory is the highest levelof the translation hierarchy.Page-Directory Pointer—Each page-directory pointer entry (PDPE) points to a page directory.Page-directory pointers are only used in PAE paging (CR4.PAE=1), and are the highest level in thelegacy page-translation hierarchy.The translation-table-entry formats and how they are used in the various forms of legacy pagetranslation are described beginning on page 121.5.2.1 CR3 RegisterThe CR3 register is used to point to the base address of the highest-level page-translation table.
Thebase address is either the page-directory pointer table or the page directory table. The CR3 registerformat depends on the form of paging being used. Figure 5-2 on page 121 shows the CR3 format when120Page Translation and Protection24593—Rev. 3.13—July 2007AMD64 Technologynormal (non-PAE) paging is used (CR4.PAE=0). Figure 5-3 shows the CR3 format when PAE pagingis used (CR4.PAE=1).3112 11Page-Directory-Table Base Address5Reserved4 3 20P PC W ReservedD TFigure 5-2.
Control Register 3 (CR3)—Non-PAE Paging Legacy-Mode315Page-Directory-Pointer-Table Base AddressFigure 5-3.4 3 20P PC W ReservedD TControl Register 3 (CR3)—PAE Paging Legacy-ModeThe CR3 register fields for legacy-mode paging are:Table Base Address Field. This field points to the starting physical address of the highest-levelpage-translation table. The size of this field depends on the form of paging used:••Normal (Non-PAE) Paging (CR4.PAE=0)—This 20-bit field occupies bits 31–12, and points to thebase address of the page-directory table.
The page-directory table is aligned on a 4-Kbyteboundary, with the low-order 12 address bits (11–0) assumed to be 0. This yields a total baseaddress size of 32 bits.PAE Paging (CR4.PAE=1)—This field is 27 bits and occupies bits 31–5. The CR3 register pointsto the base address of the page-directory-pointer table.
The page-directory-pointer table is alignedon a 32-byte boundary, with the low 5 address bits (4–0) assumed to be 0.Page-Level Writethrough (PWT) Bit. Bit 3. Page-level writethrough indicates whether the highest-level page-translation table has a writeback or writethrough caching policy.
When PWT=0, the tablehas a writeback caching policy. When PWT=1, the table has a writethrough caching policy.Page-Level Cache Disable (PCD) Bit. Bit 4. Page-level cache disable indicates whether the highest-level page-translation table is cacheable. When PCD=0, the table is cacheable. When PCD=1, the tableis not cacheable.Reserved Bits. Reserved fields should be cleared to 0 by software when writing CR3.5.2.2 Normal (Non-PAE) PagingNon-PAE paging (CR4.PAE=0) supports 4-Kbyte and 4-Mbyte physical pages, as described in thefollowing sections.Page Translation and Protection121AMD64 Technology24593—Rev. 3.13—July 20074-Kbyte Page Translation.
4-Kbyte physical-page translation is performed by dividing the 32-bitvirtual address into three fields. Each of the upper two fields are used as an index into a two-level pagetranslation hierarchy. The virtual-address fields are used as follows, and are shown in Figure 5-4:•••Bits 31–22 index into the 1024-entry page-directory table.Bits 21–12 index into the 1024-entry page table.Bits 11–0 provide the byte offset into the physical page.Virtual Address3122 21Page-DirectoryOffset12 11Page-TableOffset100Page Offset10PageDirectoryTable124 KbytePhysicalPagePageTablePTE32PhysicalAddress32PDE3112Page-Directory BaseFigure 5-4.CR34-Kbyte Non-PAE Page Translation—Legacy ModeFigure 5-5 on page 123 shows the format of the PDE (page-directory entry), and Figure 5-6 onpage 123 shows the format of the PTE (page-table entry).
Each table occupies 4 Kbytes and can hold1024 of the 32-bit table entries. The fields within these table entries are described in “PageTranslation-Table Entry Fields” on page 135.Figure 5-5 shows bit 7 cleared to 0. This bit is the page-size bit (PS), and specifies a 4-Kbyte physicalpage translation.122Page Translation and Protection24593—Rev. 3.13—July 200731AMD64 Technology12 11Page-Table Base Address9AVL876543210IGN0IP P U RG A C W / / PND T S WFigure 5-5. 4-Kbyte PDE—Non-PAE Paging Legacy-Mode3112 11Physical-Page Base Address9AVL876543210PP P U RG A D A C W / / PTD T S WFigure 5-6. 4-Kbyte PTE—Non-PAE Paging Legacy-Mode4-Mbyte Page Translation.
4-Mbyte page translation is only supported when page-size extensionsare enabled (CR4.PSE=1) and physical-address extensions are disabled (CR4.PAE=0).PSE defines a page-size bit in the 32-bit PDE format (PDE.PS). This bit is used by the processorduring page translation to support both 4-Mbyte and 4-Kbyte pages. 4-Mbyte pages are selected whenPDE.PS is set to 1, and the PDE points directly to a 4-Mbyte physical page. PTEs are not used in a 4Mbyte page translation.
If PDE.PS is cleared to 0, or if 4-Mbyte page translation is disabled, the PDEpoints to a PTE.4-Mbyte page translation is performed by dividing the 32-bit virtual address into two fields. Each fieldis used as an index into a single-level page-translation hierarchy. The virtual-address fields are used asfollows, and are shown in Figure 5-7 on page 124:••Bits 31–22 index into the 1024-entry page-directory table.Bits 21–0 provide the byte offset into the physical page.Page Translation and Protection123AMD64 Technology24593—Rev. 3.13—July 2007Virtual Address3122 21Page-DirectoryOffset0Page Offset10224 MbytePhysicalPagePageDirectoryTable40PDE31PhysicalAddress12CR3Page-Directory BaseFigure 5-7. 4-Mbyte Page Translation—Non-PAE Paging Legacy-ModeThe AMD64 architecture modifies the legacy 32-bit PDE format in PSE mode to increase physicaladdress size support to 40 bits. This increase in address size is accomplished by using bits 20–13 tohold eight additional high-order physical-address bits.
Bit 21 is reserved and must be cleared to 0.Figure 5-8 shows the format of the PDE when PSE mode is enabled. The physical-page base-addressbits are contained in a split field. The high-order, physical-page base-address bits 39–32 are located inPDE[20:13], and physical-page base-address bits 31–22 are located in PDE[31:22].3122 21 20Physical-Page Base Address [31:22] 0Figure 5-8.13 12 11PPhysical-Page Base AddressA[39:32]T9AVL876543210G1P P U RD A C W / / PD T S W4-Mbyte PDE—Non-PAE Paging Legacy-Mode5.2.3 PAE PagingPAE paging is used when physical-address extensions are enabled (CR4.PAE=1). PAE paging doublesthe size of page-translation table entries to 64 bits so that the table entries can hold larger physical124Page Translation and Protection24593—Rev.
3.13—July 2007AMD64 Technologyaddresses (up to 52 bits). The size of each table remains 4 Kbytes, which means each table can hold512 of the 64-bit entries. PAE paging also introduces a third-level page-translation table, known as thepage-directory-pointer table (PDP).The size of large pages in PAE-paging mode is 2 Mbytes rather than 4 Mbytes. PAE uses the pagedirectory page-size bit (PDE.PS) to allow selection between 4-Kbyte and 2-Mbyte page sizes. PAEautomatically uses the page-size bit, so the value of CR4.PSE is ignored by PAE paging.4-Kbyte Page Translation.
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