Volume 2 System Programming (794096), страница 44
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3.13—July 2007Virtual Address6348 47Sign Extend39 3830 2921 2012 110Page-MapPage-Directory- Page-DirectoryPage-TablePhysicalLevel-4 OffsetPointer OffsetOffsetOffsetPage Offset(PML4)999PageDirectoryPointerTablePage-MapLevel-4Table129PageDirectoryTable4 KbytePhysicalPagePageTablePTE52*52*52*PDPEPML4EPhysicalAddress52*PDE5112Page-Map Level-4Base Address*This is an architectural limit.
A given processorimplementation may support fewer bits.CR3Figure 5-17. 4-Kbyte Page Translation—Long ModeFigures 5-18 through 5-20 on page 131 and Figure 5-21 on page 131 show the long-mode 4-Kbytetranslation-table formats:••••Figure 5-18 on page 131 shows the PML4E (page-map level-4 entry) format.Figure 5-19 on page 131 shows the PDPE (page-directory-pointer entry) format.Figure 5-20 on page 131 shows the PDE (page-directory entry) format.Figure 5-21 on page 131 shows the PTE (page-table entry) format.The fields within these table entries are described in “Page-Translation-Table Entry Fields” onpage 135.Figure 5-20 on page 131 shows the PDE.PS bit (bit 7) cleared to 0, indicating a 4-Kbyte physical-pagetranslation.130Page Translation and Protection24593—Rev.
3.13—July 200763 62NXAMD64 Technology52 5132Page-Directory-Pointer Base Address(This is an architectural limit. A given implementation may support fewer bits.)Available3112 11Page-Directory-Pointer Base Address9AVL87MBZ6 5 4 3 2 1 0IP P U RG A C W / / PND T S WFigure 5-18. 4-Kbyte PML4E—Long Mode63 62NX52 5132Page-Directory Base Address(This is an architectural limit.
A given implementation may support fewer bits.)Available3112 11Page-Directory Base Address9AVL8 7 6 5 4 3 2 1 0MIP P U RB 0 G A C W / / PZND T S WFigure 5-19. 4-Kbyte PDPE—Long Mode63 62NX52 5132Page-Table Base Address(This is an architectural limit. A given implementation may support fewer bits.)Available3112 11Page-Table Base Address9AVL8IGN706 5 4 3 2 1 0IP P U RG A C W / / PND T S WFigure 5-20.
4-Kbyte PDE—Long Mode63 62NX52 5132Physical-Page Base Address(This is an architectural limit. A given implementation may support fewer bits.)Available3112 11Physical-Page Base Address9AVL87 6 5 4 3 2 1 0PP P U RG A D A C W / / PTD T S WFigure 5-21. 4-Kbyte PTE—Long ModePage Translation and Protection131AMD64 Technology24593—Rev. 3.13—July 20075.3.4 2-Mbyte Page TranslationIn long mode, 2-Mbyte physical-page translation is performed by dividing the virtual address into fivefields. Three of the fields are used as indices into the level page-translation hierarchy.
The virtualaddress fields are described as follows, and are shown in Figure 5-22 on page 132:•••••Bits 63–48 are a sign extension of bit 47 as required for canonical address forms.Bits 47–39 index into the 512-entry page-map level-4 table.Bits 38–30 index into the 512-entry page-directory-pointer table.Bits 29–21 index into the 512-entry page-directory table.Bits 20–0 provide the byte offset into the physical page.Virtual Address6348 4739 38Page-MapSign ExtendLevel-4 Table Offset(PML4)30 29Page-DirectoryPointer Offset9Page-DirectoryOffset90Page Offset219PageDirectoryPointerTablePage-MapLevel-4Table21 202 MbytePhysicalPagePageDirectoryTable52*52*PDPEPML4EPhysicalAddress52*PDE5112Page-Map Level-4Base Address*This is an architectural limit.
A given processorimplementation may support fewer bits.CR3Figure 5-22. 2-Mbyte Page Translation—Long ModeFigures 5-23 through 5-25 on page 133 show the long-mode 2-Mbyte translation-table formats (thePML4 and PDPT formats are identical to those used for 4-Kbyte page translations and are repeatedhere for clarity):•••Figure 5-23 on page 133 shows the PML4E (page-map level-4 entry) format.Figure 5-24 on page 133 shows the PDPE (page-directory-pointer entry) format.Figure 5-25 on page 133 shows the PDE (page-directory entry) format.132Page Translation and Protection24593—Rev.
3.13—July 2007AMD64 TechnologyThe fields within these table entries are described in “Page-Translation-Table Entry Fields” onpage 135. PTEs are not used in 2-Mbyte page translations.Figure 5-25 shows the PDE.PS bit (bit 7) set to 1, indicating a 2-Mbyte physical-page translation.63 62NX52 5132Page-Directory-Pointer Base Address(This is an architectural limit. A given implementation may support fewer bits.)Available3112 11Page-Directory-Pointer Base Address9AVL87MBZ6 5 4 3 2 1 0IP P U RG A C W / / PND T S WFigure 5-23.
2-Mbyte PML4E—Long Mode63 62NX52 5132Page-Directory Base Address(This is an architectural limit. A given implementation may support fewer bits.)Available3112 11Page-Directory Base Address9AVL8 7 6 5 4 3 2 1 0MIP P U RB 0 G A C W / / PZND T S WFigure 5-24. 2-Mbyte PDPE—Long Mode63NX52 5132Physical Page Base Address(This is an architectural limit. A given implementation may support fewer bits.)Available3121 20Physical Page Base AddressReserved, MBZ13 12 119PAAVLT87G1654 3 2 1 0P P U RD A C W / / PD T S WFigure 5-25.
2-Mbyte PDE—Long Mode5.3.5 1-Gbyte Page TranslationIn long mode, 1-Gbyte physical-page translation is performed by dividing the virtual address into fourfields. Two of the fields are used as indices into the level page-translation hierarchy. The virtualaddress fields are described as follows, and are shown in Figure 5-26 on page 134:••••Bits 63–48 are a sign extension of bit 47 as required for canonical address forms.Bits 47–39 index into the 512-entry page-map level-4 table.Bits 38–30 index into the 512-entry page-directory-pointer table.Bits 29–0 provide the byte offset into the physical page.Page Translation and Protection133AMD64 Technology24593—Rev.
3.13—July 2007Virtual Address6348 4739 38Page-MapSign ExtendLevel-4 Table Offset(PML4)30 290Page-DirectoryPointer Offset9Page Offset930PageDirectoryPointerTablePage-MapLevel-4Table1 GbytePhysicalPage52*52*PDPEPhysicalAddressPML4E5112*This is an architectural limit. A given processorimplementation may support fewer bits.Page-Map Level-4 Base AddressFigure 5-26.CR31-Gbyte Page Translation—Long ModeFigure 5-27 and Figure 5-28 on page 135 show the long mode 1-Gbyte translation-table formats (thePML4 format is identical to the one used for 4-Kbyte page translations and is repeated here for clarity):••Figure 5-27 shows the PML4E (page-map level-4 entry) format.Figure 5-28 shows the PDPE (page-directory-pointer entry) format.The fields within these table entries are described in “Page-Translation-Table Entry Fields” onpage 135 in the current volume.
PTEs and PDEs are not used in 1-Gbyte page translations.Figure 5-28 on page 135 shows the PDPE.PS bit (bit 7) set to 1, indicating a 1-Gbyte physical-pagetranslation.134Page Translation and Protection24593—Rev. 3.13—July 200763 62NXAMD64 Technology3252 51Page Directory Pointer Base AddressAvailable(This is an architectural limit. A given implementation may support fewer bits.)3112 11Page-Directory-Pointer Base AddressFigure 5-27.63 62NXAVL87MBZ6543210IP P U RG A C W / / PND T S W1-Gbyte PML4E—Long Mode52 5132Physical Page Base AddressAvailable(This is an architectural limit. A given implementation may support fewer bits.)31 30PhyPageBaseAddr912 11Reserved, MBZFigure 5-28.PAT9AVL876543210G1P P U RD A C W / / PD T S W1-Gbyte PDPE—Long Mode1-Gbyte Paging Feature Identification.
EDX bit 26 as returned by CPUID function 8000_0001hindicates 1-Gbyte page support. The EAX register as returned by CPUID function 8000_0019h reportsthe number of 1-Gbyte L1 TLB entries supported and EBX reports the number of 1-Gbyte L2 TLBentries. See the AMD CPUID Specification, order# 25481, for details.5.4Page-Translation-Table Entry FieldsThe page-translation-table entries contain control and informational fields used in the management ofthe virtual-memory environment.
Most fields are common across all translation table entries andmodes and occupy the same bit locations. However, some fields are located in different bit positionsdepending on the page translation hierarchical level, and other fields have different sizes depending onwhich physical-page size, physical-address size, and operating mode are selected. Although thesefields can differ in bit position or size, their meaning is consistent across all levels of the pagetranslation hierarchy and in all operating modes.Page Translation and Protection135AMD64 Technology24593—Rev. 3.13—July 20075.4.1 Field DefinitionsThe following sections describe each field within the page-translation table entries.Translation-Table Base Address Field. The translation-table base-address field points to thephysical base address of the next-lower-level table in the page-translation hierarchy.
Page datastructure tables are always aligned on 4-Kbyte boundaries, so only the address bits above bit 11 arestored in the translation-table base-address field. Bits 11–0 are assumed to be 0. The size of the fielddepends on the mode:••In normal (non-PAE) paging (CR4.PAE=0), this field specifies a 32-bit physical address.In PAE paging (CR4.PAE=1), this field specifies a 52-bit physical address.52 bits correspond to the maximum physical-address size allowed by the AMD64 architecture.
If aprocessor implementation supports fewer than the full 52-bit physical address, software must clear theunimplemented high-order translation-table base-address bits to 0. For example, if a processorimplementation supports a 40-bit physical-address size, software must clear bits 51–40 when writing atranslation-table base-address field in a page data-structure entry.Physical-Page Base Address Field. The physical-page base-address field points to the baseaddress of the translated physical page. This field is found only in the lowest level of the pagetranslation hierarchy.
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