Volume 2 System Programming (794096), страница 47
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If R/W=0, the page is read-only. A page-fault exception (#PF) occurs if an attemptis made by user software to write to a read-only page. If supervisor software attempts to write a readonly page, the outcome depends on the value of the CR0.WP bit (described below).5.6.4 Write Protect (CR0.WP) BitThe ability to write to read-only pages is governed by the processor mode and whether write protectionis enabled. If write protection is not enabled, a processor running at CPL 0, 1, or 2 can write to anyphysical page, even if it is marked as read-only.
Enabling write protection prevents supervisor codefrom writing into read-only pages, including read-only user-level pages.A page-fault exception (#PF) occurs if software attempts to write (at any privilege level) into a readonly page while write protection is enabled.142Page Translation and Protection24593—Rev. 3.13—July 20075.7AMD64 TechnologyProtection Across Paging HierarchyThe privilege level and access type specified at each level of the page-translation hierarchy have acombined effect on the protection of the translated physical page.
Enabling and disabling writeprotection further qualifies the protection effect on the physical page.Table 5-2 on page 143 shows the overall effect that privilege level and access type have on physicalpage protection when write protection is disabled (CR0.WP=0). In this case, when any translationtable entry is specified as supervisor level, the physical page is a supervisor page and can only beaccessed by software running at CPL 0, 1, or 2. Such a page allows read/write access even if all levelsof the page-translation hierarchy specify read-only access.Table 5-2.Physical-Page Protection, CR0.WP=0Page-Map Level-4EntryPage-DirectoryPointer EntryPage-DirectoryEntryPage-Table EntryU/SR/WU/SR/WU/SR/WU/SR/WS—————————S—————————S—————————S—URU—U—U—U—URU—U—U—U—URU—U—U—U—URUR/WUR/WUR/WUR/WEffective Result onPhysical PageU/SR/WSR/WUR1UR/WNote:S = Supervisor Level (CPL=0, 1, or 2), U = User Level (CPL = 3), R = Read-Only Access, R/W = Read/Write Access,— = Don’t Care.Note:1.
Supervisor-level programs can access these pages as R/W.If all table entries in the translation hierarchy are specified as user level the physical page is a userpage, and both supervisor and user software can access it. In this case the physical page is read-only ifany table entry in the translation hierarchy specifies read-only access. All table entries in thetranslation hierarchy must specify read/write access for the physical page to be read/write.Table 5-3 on page 144 shows the overall effect that privilege level and access type have on physicalpage access when write protection is enabled (CR0.WP=1). When any translation-table entry isspecified as supervisor level, the physical page is a supervisor page and can only be accessed bysupervisor software. In this case, the physical page is read-only if any table entry in the translationhierarchy specifies read-only access.
All table entries in the translation hierarchy must specifyread/write access for the supervisor page to be read/write.Page Translation and Protection143AMD64 TechnologyTable 5-3.24593—Rev. 3.13—July 2007Effect of CR0.WP=1 on Supervisor Page AccessPage-MapLevel-4EntryPageDirectoryPointerEntryPageDirectoryEntryPage TableEntryPhysicalPageR/WR/WR/WR/WR/WR————R————R————RWWWWRWNote:R = Read-Only Access Type, W = Read/Write Access Type, — = Don’t Care.Physical page is in supervisor mode, as determined by U/S settings in Table 5-2.5.7.1 Access to User Pages when CR0.WP=1As shown in Table 5-2 on page 143, read/write access to user-level pages behaves the same as whenwrite protection is disabled (CR0.WP=0), with one critical difference.
When write protection isenabled, supervisor programs cannot write into read-only user pages.5.8Effects of Segment ProtectionSegment-protection and page-protection checks are performed serially by the processor, with segmentprivilege checks performed first, followed by page-protection checks. Page-protection checks are notperformed if a segment-protection violation is found. If a violation is found during either segmentprotection or page-protection checking, an exception occurs and no memory access is performed.Segment-protection violations cause either a general-protection exception (#GP) or a stack exception(#SS) to occur.
Page-protection violations cause a page-fault exception (#PF) to occur.144Page Translation and Protection24593—Rev. 3.13—July 20076AMD64 TechnologySystem-Management InstructionsSystem-management instructions provide control over the resources used to manage the processoroperating environment. This includes memory management, memory protection, task management,interrupt and exception handling, system-management mode, software debug and performanceanalysis, and model-specific features. Most instructions used to access these resources are privilegedand can only be executed while the processor is running at CPL=0, although some instructions can beexecuted at any privilege level.Table 6-1 summarizes the instructions used for system management.
These include all privilegedinstructions, instructions whose privilege requirement is under the control of system software, nonprivileged instructions that are used primarily by system software, and instructions used to transfercontrol to system software. Most of the instructions listed in Table 6-1 are summarized in this chapter,although a few are introduced elsewhere in this manual, as indicated in the Reference column ofTable 6-1.For details on individual system instructions, see “System Instruction Reference” in Volume 3.Table 6-1. System Management InstructionsPrivilegeMnemonicNameCPL=0O/S1AnyXReference“Adjusting Access Rights” onpage 154ARPLAdjust Requestor Privilege LevelCLIClear Interrupt FlagCLTSClear Task-Switched Flag in CR0X“CLTS Instruction” on page 151HLTHaltX“Processor Halt” on page 154INT3Interrupt to Debug VectorINVDInvalidate CachesX“Cache Management” onpage 155INVLPGInvalidate TLB EntryX“TLB Invalidation” on page 155IRETxInterrupt Return (all forms)X“Returning From InterruptProcedures” on page 236LARLoad Access-Rights ByteX“Checking Access Rights” onpage 154LGDTLoad Global-Descriptor-TableRegisterXLIDTLoad Interrupt-Descriptor-TableRegisterX“CLI and STI Instructions” onpage 152XX“Breakpoint Instruction (INT3)” onpage 338“LGDT and LIDT Instructions” onpage 153Note:1.
The operating system controls the privilege required to use the instruction.System-Management Instructions145AMD64 Technology24593—Rev. 3.13—July 2007Table 6-1. System Management Instructions (continued)PrivilegeMnemonicNameCPL=0O/S1AnyReferenceLLDTLoad Local-Descriptor-TableRegisterX“LLDT and LTR Instructions” onpage 153LMSWLoad Machine-Status WordX“LMSW and SMSW Instructions”on page 151LSLLoad Segment LimitLTRLoad Task RegisterX“LLDT and LTR Instructions” onpage 153MOV CRnMove to/from Control RegistersX“MOV CRn Instructions” onpage 151MOV DRnMove to/from Debug RegistersX“Accessing Debug Registers” onpage 152RDMSRRead Model-Specific RegisterX“RDMSR and WRMSRInstructions” on page 152RDPMCRead Performance-MonitorCounterX“RDPMC Instruction” on page 152RDTSCRead Time-Stamp CounterX“RDTSC Instruction” on page 152RDTSCPRead Time-Stamp Counter andProcessor IDX“RDTSCP Instruction” onpage 152RSMReturn from SystemManagement ModeXSGDTStore Global-Descriptor-TableRegisterXSIDTStore Interrupt-Descriptor-TableRegisterXSLDTStore Local-Descriptor-TableRegisterX“SLDT and STR Instructions” onpage 153SMSWStore Machine-Status WordX“LMSW and SMSW Instructions”on page 151STISet Interrupt FlagSTRStore Task RegisterSWAPGSSwap GS and KernelGSbaseRegistersSYSCALLFast System CallX“Checking Segment Limits” onpage 154“Leaving SMM” on page 284“SGDT and SIDT Instructions” onpage 153“CLI and STI Instructions” onpage 152XX“SLDT and STR Instructions” onpage 153“SWAPGS Instruction” onpage 150XX“SYSCALL and SYSRET” onpage 148Note:1.
The operating system controls the privilege required to use the instruction.146System-Management Instructions24593—Rev. 3.13—July 2007AMD64 TechnologyTable 6-1. System Management Instructions (continued)PrivilegeMnemonicNameCPL=0O/S1SYSENTER System CallAnyXReference“SYSENTER and SYSEXIT(Legacy Mode Only)” on page 150SYSEXITSystem ReturnXSYSRETFast System ReturnXUD2Undefined OperationXVERRVerify Segment for ReadsXVERWVerify Segment for WritesXWBINVDWriteback and Invalidate CachesX“Cache Management” onpage 155WRMSRWrite Model-Specific RegisterX“RDMSR and WRMSRInstructions” on page 152“SYSCALL and SYSRET” onpage 148“System Instruction Reference” inVolume 3“Checking Read/Write Rights” onpage 154Note:1.
The operating system controls the privilege required to use the instruction.The following instructions are summarized in this chapter but are not categorized as systeminstructions, because of their importance to application programming:•••The CPUID instruction returns information critical to system software in initializing the operatingenvironment. It is fully described in “Processor Feature Identification” on page 61.The PUSHF and POPF instructions set and clear certain RFLAGS bits depending on the processoroperating mode and privilege level.
These dependencies are described in “POPF and PUSHFInstructions” on page 152.The MOV, PUSH, and POP instructions can be used to load and store segment registers, asdescribed in “MOV, POP, and PUSH Instructions” on page 153.6.1Fast System Call and ReturnOperating systems can use both paging and segmentation to implement protected memory models.Segment descriptors provide the necessary memory protection and privilege checking for segmentaccesses. By setting segment-descriptor fields appropriately, operating systems can enforce accessrestrictions as needed.A disadvantage of segment-based protection and privilege checking is the overhead associated withloading a new segment selector (and its corresponding descriptor) into a segment register.
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