Volume 2 System Programming (794096), страница 61
Текст из файла (страница 61)
3.13—July 2007When a non-debug exception occurs (or when a string instruction is interrupted), the processornormally sets RFLAGS.RF to 1 in the RFLAGS image that is pushed on the interrupt stack. Asubsequent IRET back to the interrupted program pops the RFLAGS image off the stack and into theRFLAGS register, with RFLAGS.RF=1. The interrupted instruction executes without causing aninstruction breakpoint, after which the processor clears RFLAGS.RF to 0.However, when a #DB exception occurs, the processor clears RFLAGS.RF to 0 in the RFLAGS imagethat is pushed on the interrupt stack.
The #DB handler has two options:••Disable the instruction breakpoint completely.Set RFLAGS.RF to 1 in the interrupt-stack rFLAGS image. The instruction breakpoint condition isignored immediately after the IRET, but reoccurs if the instruction address is accessed later, as canoccur in a program loop.8.2.3 NMI—Non-Maskable-Interrupt Exception (Vector 2)An NMI exception occurs as a result of system logic signalling a non-maskable interrupt to theprocessor.Error Code Returned. None.Program Restart.
NMI is an interrupt. The processor recognizes an NMI at an instruction boundary.The saved instruction pointer points to the instruction immediately following the boundary where theNMI was recognized.Masking. NMI cannot be masked. However, when an NMI is recognized by the processor,recognition of subsequent NMIs are disabled until an IRET instruction is executed.8.2.4 #BP—Breakpoint Exception (Vector 3)A #BP exception occurs when an INT3 instruction is executed. The INT3 is normally used by debugsoftware to set instruction breakpoints by replacing instruction-opcode bytes with the INT3 opcode.#BP cannot be disabled.Error Code Returned.
None.Program Restart. #BP is a trap-type exception. The saved instruction pointer points to the byte afterthe INT3 instruction. This location can be the start of the next instruction. However, if the INT3 is usedto replace the first opcode bytes of an instruction, the restart location is likely to be in the middle of aninstruction. In the latter case, the debug software must replace the INT3 byte with the correctinstruction byte. The saved RIP instruction pointer must then be decremented by one before returningto the interrupted program.
This allows the program to be restarted correctly on the interruptedinstruction boundary.210Exceptions and Interrupts24593—Rev. 3.13—July 2007AMD64 Technology8.2.5 #OF—Overflow Exception (Vector 4)An #OF exception occurs as a result of executing an INTO instruction while the overflow bit inRFLAGS is set to 1 (RFLAGS.OF=1).#OF cannot be disabled.Error Code Returned. None.Program Restart. #OF is a trap-type exception. The saved instruction pointer points to theinstruction following the INTO instruction that caused the #OF.8.2.6 #BR—Bound-Range Exception (Vector 5)A #BR exception can occur as a result of executing the BOUND instruction.
The BOUND instructioncompares an array index (first operand) with the lower bounds and upper bounds of an array (secondoperand). If the array index is not within the array boundary, the #BR occurs.#BR cannot be disabled.Error Code Returned. None.Program Restart. #BR is a fault-type exception. The saved instruction pointer points to the BOUNDinstruction that caused the #BR.8.2.7 #UD—Invalid-Opcode Exception (Vector 6)A #UD exception occurs when an attempt is made to execute an invalid or undefined opcode.
Thevalidity of an opcode often depends on the processor operating mode. A #UD occurs under thefollowing conditions:•••••••••Execution of any reserved or undefined opcode in any mode.Execution of the UD2 instruction.Use of the LOCK prefix on an instruction that cannot be locked.Use of the LOCK prefix on a lockable instruction with a non-memory target location.Execution of an instruction with an invalid-operand type.Execution of the SYSENTER or SYSEXIT instructions in long mode.Execution of any of the following instructions in 64-bit mode: AAA, AAD, AAM, AAS, BOUND,CALL (opcode 9A), DAA, DAS, DEC, INC, INTO, JMP (opcode EA), LDS, LES, POP (DS, ES,SS), POPA, PUSH (CS, DS, ES, SS), PUSHA, SALC.Execution of the ARPL, LAR, LLDT, LSL, LTR, SLDT, STR, VERR, or VERW instructions whenprotected mode is not enabled, or when virtual-8086 mode is enabled.Execution of any 128-bit media instruction when CR4.OSFXSR is cleared to 0.
(For furtherinformation, see “FXSAVE/FXRSTOR Support (OSFXSR) Bit” on page 49.Exceptions and Interrupts211AMD64 Technology••••24593—Rev. 3.13—July 2007Execution of any 128-bit media instruction (uses XMM registers), or 64-bit media instruction(uses MMX™ registers) when CR0.EM = 1.Execution of any 128-bit media floating-point instruction (uses XMM registers) that causes anumeric exception when CR4.OSXMMEXCPT = 0.Use of the DR4 or DR5 debug registers when CR4.DE = 1.Execution of RSM when not in SMM mode.See the specific instruction description (in the other volumes) for additional information on invalidconditions.#UD cannot be disabled.Error Code Returned. None.Program Restart. #UD is a fault-type exception. The saved instruction pointer points to theinstruction that caused the #UD.8.2.8 #NM—Device-Not-Available Exception (Vector 7)A #NM exception occurs under any of the following conditions:••••An FWAIT/WAIT instruction is executed when CR0.MP=1 and CR0.TS=1.Any x87 instruction other than FWAIT is executed when CR0.EM=1.Any x87 instruction is executed when CR0.TS=1.
The CR0.MP bit controls whether theFWAIT/WAIT instruction causes an #NM exception when TS=1.Any 128-bit or 64-bit media instruction when CR0.TS=1.#NM can be enabled or disabled under the control of the CR0.MP, CR0.EM, and CR0.TS bits asdescribed above. See “CR0 Register” on page 42 for more information on the CR0 bits used to controlthe #NM exception.Error Code Returned.
None.Program Restart. #NM is a fault-type exception. The saved instruction pointer points to theinstruction that caused the #NM.8.2.9 #DF—Double-Fault Exception (Vector 8)A #DF exception can occur when a second exception occurs during the handling of a prior (first)exception or interrupt handler.Usually, the first and second exceptions can be handled sequentially without resulting in a #DF. In thiscase, the first exception is considered benign, as it does not harm the ability of the processor to handlethe second exception.In some cases, however, the first exception adversely affects the ability of the processor to handle thesecond exception.
These exceptions contribute to the occurrence of a #DF, and are called contributory212Exceptions and Interrupts24593—Rev. 3.13—July 2007AMD64 Technologyexceptions. If a contributory exception is followed by another contributory exception, a double-faultexception occurs. Likewise, if a page fault is followed by another page fault or a contributoryexception, a double-fault exception occurs.Table 8-3 on page 213 shows the conditions under which a #DF occurs. Page faults are either benign orcontributory, and are listed separately. See the “Class” column in Table 8-2 on page 208 forinformation on whether an exception is benign or contributory.Table 8-3.Double-Fault Exception ConditionsFirst Interrupting EventSecond Interrupting EventContributory Exceptions• Divide-by-Zero-Error Exception• Invalid-TSS Exception• Segment-Not-Present Exception• Stack Exception• General-Protection ExceptionInvalid-TSS ExceptionSegment-Not-Present ExceptionStack ExceptionGeneral-Protection ExceptionPage Fault ExceptionPage Fault ExceptionInvalid-TSS ExceptionSegment-Not-Present ExceptionStack ExceptionGeneral-Protection ExceptionIf a third interrupting event occurs while transferring control to the #DF handler, the processor shutsdown.
Only an NMI, RESET, or INIT can restart the processor in this case. However, if the processorshuts down as it is executing an NMI handler, the processor can only be restarted with RESET or INIT.#DF cannot be disabled.Error Code Returned. Zero.Program Restart. #DF is an abort-type exception. The saved instruction pointer is undefined, and theprogram cannot be restarted.8.2.10 Coprocessor-Segment-Overrun Exception (Vector 9)This interrupt vector is reserved.
It is for a discontinued exception originally used by processors thatsupported external x87-instruction coprocessors. On those processors, the exception condition iscaused by an invalid-segment or invalid-page access on an x87-instruction coprocessor-instructionoperand. On current processors, this condition causes a general-protection exception to occur.Error Code Returned.
Not applicable.Program Restart. Not applicable.Exceptions and Interrupts213AMD64 Technology24593—Rev. 3.13—July 20078.2.11 #TS—Invalid-TSS Exception (Vector 10)A #TS exception occurs when an invalid reference is made to a segment selector as part of a taskswitch. A #TS also occurs during a privilege-changing control transfer (through a call gate or aninterrupt gate), if a reference is made to an invalid stack-segment selector located in the TSS.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
