Volume 2 System Programming (794096), страница 63
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None. Exception information is provided by the x87 status-word register. See“x87 Floating-Point Programming” in Volume 1 for more information on using this register.Program Restart. #MF is a fault-type exception. The #MF exception is not precise, because multipleinstructions and exceptions can occur before the #MF handler is invoked. Also, the saved instructionpointer does not point to the instruction that caused the exception resulting in the #MF.
Instead, thesaved instruction pointer points to the x87 floating-point instruction or FWAIT/WAIT instruction thatis about to be executed when the #MF occurs. The address of the last instruction that caused an x87floating-point exception is in the x87 instruction-pointer register. See “x87 Floating-PointProgramming” in Volume 1 for information on accessing this register.Masking.
Each type of x87 floating-point exception can be masked by setting the appropriate bits inthe x87 control-word register. See “x87 Floating-Point Programming” in Volume 1 for moreinformation on using this register.#MF can also be disabled by clearing the CR0.NE bit to 0. See “Numeric Error (NE) Bit” on page 44for more information on using this bit.8.2.17 #AC—Alignment-Check Exception (Vector 17)An #AC exception occurs when an unaligned-memory data reference is performed while alignmentchecking is enabled.After a processor reset, #AC exceptions are disabled.
Software enables the #AC exception by settingthe following register bits:••CR0.AM=1.RFLAGS.AC=1.When the above register bits are set, an #AC can occur only when CPL=3. #AC never occurs whenCPL < 3.Table 8-7 on page 220 lists the data types and the alignment boundary required to avoid an #ACexception when the mechanism is enabled.Exceptions and Interrupts219AMD64 Technology24593—Rev. 3.13—July 2007Table 8-7.
Data-Type AlignmentSupported Data TypeRequired Alignment(Byte Boundary)Word2Doubleword4Quadword8Bit string2, 4 or 8 (depends on operand size)128-bit media1664-bit media8Segment selector232-bit near pointer432-bit far pointer248-bit far pointer4x87 Floating-point single-precision4x87 Floating-point double-precision8x87 Floating-point extended-precision8x87 Floating-point save areas2 or 4 (depends on operand size)Error Code Returned. Zero.Program Restart. #AC is a fault-type exception.
The saved instruction pointer points to theinstruction that caused the #AC.8.2.18 #MC—Machine-Check Exception (Vector 18)The #MC exception is model specific. Processor implementations are not required to support the #MCexception, and those implementations that do support #MC can vary in how the #MC exceptionmechanism works.The exception is enabled by setting CR4.MCE to 1.
The machine-check architecture can includemodel-specific masking for controlling the reporting of some errors. Refer to Chapter 9, “MachineCheck Mechanism,” for more information.Error Code Returned. None. Error information is provided by model-specific registers (MSRs)defined by the machine-check architecture.Program Restart.
#MC is an abort-type exception. There is no reliable way to restart the program. Ifthe EIPV flag (EIP valid) is set in the MCG_Status MSR, the saved CS and rIP point to the instructionthat caused the error. If EIP is clear, the CS:rIP of the instruction causing the failure is not known or themachine check is not related to a specific instruction.220Exceptions and Interrupts24593—Rev.
3.13—July 2007AMD64 Technology8.2.19 #XF—SIMD Floating-Point Exception (Vector 19)The #XF exception is used to handle unmasked 128-bit media floating-point exceptions. A #XFexception occurs when all of the following conditions are true:•••A 128-bit media floating-point exception occurs.
The exception causes the processor to set theappropriate exception-status bit in the MXCSR register to 1.The exception-mask bit in the MXCSR that corresponds to the 128-bit media floating-pointexception is clear (=0).CR4.OSXMMEXCPT=1, indicating that the operating system supports handling of 128-bit mediafloating-point exceptions.The exception-mask bits are used by software to specify the handling of 128-bit media floating-pointexceptions.
When the corresponding mask bit is cleared to 0, an exception occurs under the control ofthe CR4.OSXMMEXCPT bit. However, if the mask bit is set to 1, the 128-bit media floating-point unitresponds in a default manner and execution proceeds normally.The CR4.OSXMMEXCPT bit specifies the interrupt vector to be taken when an unmasked 128-bitmedia floating-point exception occurs. When CR4.OSXMMEXCPT=1, the #XF interrupt vector istaken when an exception occurs. When CR4.OSXMMEXCPT=0, the #UD (undefined opcode)interrupt vector is taken when an exception occurs.The 128-bit media floating-point exceptions reported by the #XF exception are (includingmnemonics):••••••IE—Invalid-operation exception (also called #I).DE—Denormalized-operand exception (also called #D).ZE—Zero-divide exception (also called #Z).OE—Overflow exception (also called #O).UE—Underflow exception (also called #U).PE—Precision exception (also called #P or inexact-result exception).Each type of 128-bit media floating-point exception can be masked by setting the appropriate bits inthe MXCSR register.
#XF can also be disabled by clearing the CR4.OSXMMEXCPT bit to 0.Error Code Returned. None. Exception information is provided by the 128-bit media floating-pointMXCSR register. See “128-Bit Media and Scientific Programming” in Volume 1 for more informationon using this register.Program Restart. #XF is a fault-type exception. Unlike the #MF exception, the #XF exception isprecise. The saved instruction pointer points to the instruction that caused the #XF.8.2.20 User-Defined Interrupts (Vectors 32–255)User-defined interrupts can be initiated either by system logic or software. They occur when:Exceptions and Interrupts221AMD64 Technology••24593—Rev.
3.13—July 2007System logic signals an external interrupt request to the processor. The signalling mechanism andthe method of communicating the interrupt vector to the processor are implementation dependent.Software executes an INTn instruction. The INTn instruction operand provides the interrupt vectornumber.Both methods can be used to initiate an interrupt into vectors 0 through 255. However, because vectors0 through 31 are defined or reserved by the AMD64 architecture, software should not use vectors inthis range for purposes other than their defined use.Error Code Returned.
None.Program Restart. The saved instruction pointer depends on the interrupt source:••External interrupts are recognized on instruction boundaries. The saved instruction pointer pointsto the instruction immediately following the boundary where the external interrupt wasrecognized.If the interrupt occurs as a result of executing the INTn instruction, the saved instruction pointerpoints to the instruction after the INTn.Masking. The ability to mask user-defined interrupts depends on the interrupt source:••External interrupts can be masked using the rFLAGS.IF bit.
Setting rFLAGS.IF to 1 enablesexternal interrupts, while clearing rFLAGS.IF to 0 inhibits them.Software interrupts (initiated by the INTn instruction) cannot be disabled.8.3Exceptions During a Task SwitchAn exception can occur during a task switch while loading a segment selector. Page faults can alsooccur when accessing a TSS. In these cases, the hardware task-switch mechanism completes loadingthe new task state from the TSS, and then triggers the appropriate exception mechanism. No otherchecks are performed. When this happens, the saved instruction pointer points to the first instruction inthe new task.In long mode, an exception cannot occur during a task switch, because the hardware task-switchmechanism is disabled.8.4Error CodesThe processor exception-handling mechanism reports error and status information for someexceptions using an error code.
The error code is pushed onto the stack by the exception-mechanismduring the control transfer into the exception handler. The error code has two formats: a selectorformat for most error-reporting exceptions, and a page-fault format for page faults. These formats aredescribed in the following sections.222Exceptions and Interrupts24593—Rev. 3.13—July 2007AMD64 Technology8.4.1 Selector-Error CodeFigure 8-2 shows the format of the selector-error code.3116 15Reserved32TISelector Index1 0I ED XT TFigure 8-2. Selector Error CodeThe information reported by the selector-error code includes:•EXT—Bit 0. If this bit is set to 1, the exception source is external to the processor.
If cleared to 0,the exception source is internal to the processor.•IDT—Bit 1. If this bit is set to 1, the error-code selector-index field references a gate descriptorlocated in the interrupt-descriptor table (IDT). If cleared to 0, the selector-index field references adescriptor in either the global-descriptor table (GDT) or local-descriptor table (LDT), as indicatedby the TI bit.TI—Bit 2. If this bit is set to 1, the error-code selector-index field references a descriptor in theLDT. If cleared to 0, the selector-index field references a descriptor in the GDT. The TI bit isrelevant only when the IDT bit is cleared to 0.Selector Index—Bits 15–3. The selector-index field specifies the index into either the GDT, LDT,or IDT, as specified by the IDT and TI bits.••Some exceptions return a zero in the selector-error code.8.4.2 Page-Fault Error CodeFigure 8-3 shows the format of the page-fault error code.314ReservedFigure 8-3.3 2 1 0R U RI/D S / / PV S WPage-Fault Error CodeThe information reported by the page-fault error code includes:••P—Bit 0.
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