Volume 2 System Programming (794096), страница 77
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When theseinstructions are supported, system software must set CR4.OSFXSR=1 to let the processor know thatthe software uses these instructions. When the processor detects CR4.OSFXSR=1, it allows executionof the 128-bit media instructions. If system software does not set CR4.OSFXSR to 1, attempts toexecute 128-bit media instructions cause an invalid-opcode exception (#UD).System software must also clear the CR0.EM (emulate coprocessor) bit to 0, otherwise an attempt toexecute a 128-bit media instruction causes a #UD exception.System software should also set the CR0.MP (monitor coprocessor) bit to 1. When CR0.EM=0 andCR0.MP=1, all media instructions, x87 instructions, and the FWAIT/WAIT instructions cause adevice-not-available exception (#NM) when the CR0.TS bit is set.
System software can use the #NMexception to perform lazy context switching, saving and restoring media and x87 state only whennecessary after a task switch. See “CR0 Register” on page 42 for more information.System software must supply an exception handler if unmasked 128-bit media floating-pointexceptions are allowed to occur. When an unmasked exception is detected, the processor transferscontrol to the SIMD floating-point exception (#XF) handler provided by the operating system.
Systems o f t wa r e m u s t l e t t h e p r o c e s s o r k n ow t h a t t h e # X F h a n d l er i s ava i l a b l e by s e t t i n gCR4.OSXMMEXCPT to 1. If this bit is set to 1, the processor transfers control to the #XF handlerwhen it detects an unmasked exception, otherwise a #UD exception occurs. When the processordetects a masked exception, it handles it in a default manner regardless of the CR4.OSXMMEXCPTvalue.288128-Bit, 64-Bit, and x87 Programming24593—Rev. 3.13—July 200711.4AMD64 TechnologyMedia and x87 Processor StateThe media and x87 processor state includes the contents of the registers used by 128-bit media, 64-bitmedia, and x87 instructions.
System software that supports such applications must be capable ofsaving and restoring these registers.11.4.1 128-Bit Media StateFigure 11-1 on page 290 shows the registers whose contents are affected by execution of 128-bit mediainstructions. These include:••xmm0–xmm15—Sixteen 128-bit media registers.
In legacy and compatibility modes, softwareaccess is limited to the first eight registers, XMM0–XMM7.MXCSR—The 32-bit control and status register.All of the above registers are visible to 128-bit media application software. Refer to “128-Bit Mediaand Scientific Programming” in Volume 1 for more information on these registers.128-Bit, 64-Bit, and x87 Programming289AMD64 Technology24593—Rev. 3.13—July 2007XMM Data Registers1270xmm0xmm1xmm2xmm3xmm4xmm5xmm6xmm7xmm8xmm9xmm10xmm11xmm12xmm13xmm14xmm15128-Bit Media Control and Status RegisterMXCSR310513-270.epsFigure 11-1.128-Bit Media-Instruction State11.4.2 64-Bit Media StateFigure 11-2 on page 291 shows the register contents that are affected by execution of 64-bit mediainstructions. These registers include:•••mmx0–mmx7—Eight 64-bit media registers.FSW—Two fields (TOP and ES) in the 16-bit x87 status word register.FTW—The 16-bit x87 tag word.290128-Bit, 64-Bit, and x87 Programming24593—Rev.
3.13—July 2007AMD64 TechnologyMMX Data Registers7964 630mmx0fpr0mmx1fpr1mmx2fpr2mmx3fpr3mmx4fpr4mmx5fpr5mmx6fpr6mmx7fpr7TOP ESVisible to application softwareWritten by processor hardwarex87 Status WordFSWx87 Tag WordFTW150513-272.epsFigure 11-2. 64-Bit Media-Instruction StateThe 64-bit media instructions and x87 floating-point instructions share the same physical dataregisters. Figure 11-2 shows how the 64-bit registers (MMX0–MMX7) are aliased onto the low 64 bitsof the 80-bit x87 floating-point physical data registers (FPR0–FPR7). Refer to “64-Bit MediaProgramming” in Volume 1 for more information on these registers.Of the registers shown in Figure 11-2, only the eight 64-bit MMX registers are visible to 64-bit mediaapplication software. The processor maintains the contents of the two fields of the x87 status word—top-of-stack-pointer (TOP) and exception summary (ES)—and the 16-bit x87 tag word duringexecution of 64-bit media instructions, as described in “Actions Taken on Executing 64-Bit MediaInstructions” in Volume 1.64-bit media instructions do not generate x87 floating-point exceptions, nor do they set any statusflags.
However, 64-bit media instructions can trigger an unmasked floating-point exception caused bya previously executed x87 instruction. 64-bit media instructions do this by reading the x87 FSW.ES bitto determine whether such an exception is pending.128-Bit, 64-Bit, and x87 Programming291AMD64 Technology24593—Rev.
3.13—July 200711.4.3 x87 StateFigure 11-3 on page 293 shows the registers whose contents are affected by execution of x87 floatingpoint instructions. These registers include:•••••••fpr0–fpr7—Eight 80-bit floating-point physical registers.FCW—The 16-bit x87 control word register.FSW—The 16-bit x87 status word register.FTW—The 16-bit x87 tag word.Last x87 Instruction Pointer—This value is a pointer (32-bit, 48-bit, or 64-bit, depending oneffective operand size and mode) to the last non-control x87 floating-point instruction executed.Last x87 Data Pointer—The pointer (32-bit, 48-bit, or 64-bit, depending on effective operand sizeand mode) to the data operand referenced by the last non-control x87 floating-point instructionexecuted, if that instruction referenced memory; if it did not, then this value is implementationdependent.Last x87 Opcode—An 11-bit permutation of the instruction opcode from the last non-control x87floating-point instruction executed.Of the registers shown in Figure 11-3 on page 293, only FPR0–FPR7, FCW, and FSW are directlyupdated by x87 application software.
The processor maintains the contents of the FTW, instruction anddata pointers, and opcode registers during execution of x87 instructions. Refer to “Registers” inVolume 1 for more information on these registers.The 11-bit instruction opcode register holds a permutation of the two-byte instruction opcode from thelast non-control x87 instruction executed by the processor. (For a definition of non-control x87instruction, see “Control” in Volume 1.) The opcode field is formed as follows:••Opcode Register Field[10:8] = First x87 opcode byte[2:0].Opcode Register Field[7:0] = Second x87 opcode byte[7:0].For example, the x87 opcode D9 F8h is stored in the opcode register as 001_1111_1000b. The loworder three bits of the first opcode byte, D9h (1101_1001b), are stored in opcode-register bits 10–8.The second opcode byte, F8h (1111_1000b), is stored in bits 7–0 of the opcode register.
The highorder five bits of the first opcode byte (1101_1b) are not needed because they are identical for all x87instructions.292128-Bit, 64-Bit, and x87 Programming24593—Rev. 3.13—July 2007AMD64 Technologyx87 Data Registers790fpr0fpr1fpr2fpr3fpr4fpr5fpr6fpr7x87 Control WordFCWWordControlx87 Status WordFSWWordStatusx87 Tag WordFTWTagWord150Last x87 Instruction PointerLast x87 Data Pointer63Opcode100513-271.epsFigure 11-3.
x87-Instruction State11.4.4 Saving Media and x87 Processor StateIn most cases, operating systems, exception handlers, and device drivers should save and restore themedia and/or x87 processor state between task switches or other interventions in the execution of 128bit, 64-bit, or x87 procedures. Application programs are also free to save and restore state at any time.In general, system software should use the FXSAVE and FXRSTOR instructions to save and restorethe entire media and x87 processor state. The FSAVE/FNSAVE and FRSTOR instructions can be usedfor saving and restoring the x87 state. Because the 64-bit media registers are physically aliased ontothe x87 registers, the FSAVE/FNSAVE and FRSTOR instructions can also be used to save and restorethe 64-bit media state.
However, FSAVE/FNSAVE and FRSTOR do not save or restore the 128-bitmedia state.128-Bit, 64-Bit, and x87 Programming293AMD64 Technology24593—Rev. 3.13—July 2007FSAVE/FNSAVE and FRSTOR Instructions. The FSAVE/FNSAVE and FRSTOR instructions saveand restore the entire register state for 64-bit media instructions and x87 floating-point instructions.The FSAVE instruction stores the register state, but only after handling any pending unmasked-x87floating-point exceptions. The FNSAVE instruction stores the register state but skips the reporting andhandling of these exceptions.
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