Volume 2 System Programming (794096), страница 79
Текст из файла (страница 79)
Deriving FSAVE Tag Field from FXSAVE Tag FieldEncodedFXSAVETag FieldExponentAll 0s1 (Valid)Neitherall 0snor all 1sInteger Bit2Fraction1Type of ValueEquivalentFSAVETag Field0All 0sZero01 (Zero)0Not all 0sDenormal1All 0s1Not all 0s0110 (Empty)don’t care10 (Special)Unnormaldon’t careNormal00 (Valid)Pseudo Infinityor Pseudo NaN0All 1sPseudo DenormalAll 0sInfinityNot all 0sNaN10 (Special)Empty11 (Empty)Note:1. Bits 62–0 of the significand. Bit 62, the most-significant bit of the fraction, is also called the M bit.2. Bit 63 of the significand, also called the J bit.Performance Considerations. When system software supports multi-tasking, it must be able to savethe processor state for one task and load the state for another.
For performance reasons, the mediaand/or x87 processor state is usually saved and loaded only when necessary. System software can saveand load this state at the time a task switch occurs. However, if the new task does not use the state,loading the state is unnecessary and reduces performance.The task-switch bit (CR0.TS) is provided as a lazy context-switch mechanism that allows systemsoftware to save and load the processor state only when necessary. When CR0.TS=1, a device-notavailable exception (#NM) occurs when an attempt is made to execute a 128-bit media, 64-bit media,or x87 instruction.
System software can use the #NM exception handler to save the state of theprevious task, and restore the state of the current task. Before returning from the exception handler tothe media or x87 instruction, system software must clear CR0.TS to 0 to allow the instruction to beexecuted. Using this approach, the processor state is saved only when the registers are used.In legacy mode, the hardware task-switch mechanism sets CR0.TS=1 during a task switch (see “TaskSwitched (TS) Bit” on page 44 for more information).
In long mode, the hardware task-switching isnot supported, and the CR0.TS bit is not set by the processor. Instead, the architecture assumes thatsystem software handles all task-switching and state-saving functions. If CR0.TS is to be used in longmode for controlling the save and restore of media or x87 state, system software must set and clear itexplicitly.304128-Bit, 64-Bit, and x87 Programming24593—Rev. 3.13—July 200712AMD64 TechnologyTask ManagementThis chapter describes the hardware task-management features.
All of the legacy x86 taskmanagement features are supported by the AMD64 architecture in legacy mode, but most features arenot available in long mode. Long mode, however, requires system software to initialize and maintaincertain task-management resources.
The details of these resource-initialization requirements for longmode are discussed in “Task-Management Resources” on page 306.12.1Hardware Multitasking OverviewA task (also called a process) is a program that the processor can execute, suspend, and later resumeexecuting at the point of suspension. During the time a task is suspended, other tasks are allowed toexecute. Each task has its own execution space, consisting of:•••••••••Code segment and instruction pointer.Data segments.Stack segments for each privilege level.General-purpose registers.rFLAGS register.Local-descriptor table.Task register, and a link to the previously-executed task.I/O-permission and interrupt-permission bitmaps.Pointer to the page-translation tables (CR3).The state information defining this execution space is stored in the task-state segment (TSS)maintained for each task.Support for hardware multitasking is provided in legacy mode.
Hardware multitasking providesautomated mechanisms for switching tasks, saving the execution state of the suspended task, andrestoring the execution state of the resumed task. When hardware multitasking is used to switch tasks,the processor takes the following actions:••••Suspends execution of the task, allowing any executing instructions to complete and save theirresults.Saves the task execution state in the task TSS.Loads the execution state for the new task from its TSS.Begins executing the new task at the location specified in the new task TSS.Software can switch tasks by branching to a new task using the CALL or JMP instructions. Exceptionsand interrupts can also switch tasks if the exception or interrupt handlers are themselves separate tasks.IRET can be used to return to an earlier task.Task Management305AMD64 Technology12.224593—Rev.
3.13—July 2007Task-Management ResourcesThe hardware-multitasking features are available when protected mode is enabled (CR0.PE=1).Protected-mode software execution, by definition, occurs as part of a task. While system software isnot required to use the hardware-multitasking features, it is required to initialize certain taskmanagement resources for at least one task (the current task) when running in protected mode. Thissingle task is needed to establish the protected-mode execution environment.
The resources that mustbe initialized are:••••Task-State Segment (TSS)—A segment that holds the processor state associated with a task.TSS Descriptor—A segment descriptor that defines the task-state segment.TSS Selector—A segment selector that references the TSS descriptor located in the GDT.Task Register—A register that holds the TSS selector and TSS descriptor for the current task.Figure 12-1 on page 307 shows the relationship of these resources to each other in both 64-bit and 32bit operating environments.306Task Management24593—Rev. 3.13—July 2007AMD64 TechnologyGlobal-DescriptorTableTSS DescriptorTask Register (Visible)15Task Register (Hidden From Software)0TSS Selector64-Bit or 32-Bit Base Address32-Bit LimitAttributes+Task-State SegmentI/O-Permission BitmapInterrupt-Redirection BitmapI/O-Bitmap Base Address513-254.epsFigure 12-1.
Task-Management ResourcesA fifth resource is available in legacy mode for use by system software that uses the hardwaremultitasking mechanism to manage more than one task:•Task-Gate Descriptor—This form of gate descriptor holds a reference to a TSS descriptor and isused to control access between tasks.Task Management307AMD64 Technology24593—Rev.
3.13—July 2007The task-management resources are described in the following sections.12.2.1 TSS SelectorTSS selectors are selectors that point to task-state segment descriptors in the GDT. Their format isidentical to all other segment selectors, as shown in Figure 12-2.153Selector Index210TIRPLBits MnemonicDescription15-3Selector Index2TITable Indicator1-0 RPLRequestor Privilege LevelFigure 12-2.Task-Segment SelectorThe selector format consists of the following fields:Selector Index. Bits 15–3. The selector-index field locates the TSS descriptor in the global-descriptor table.Table Indicator (TI) Bit.
Bit 2. The TI bit must be cleared to 0, which indicates that the GDT is used.TSS descriptors cannot be located in the LDT. If a reference is made to a TSS descriptor in the LDT, ageneral-protection exception (#GP) occurs.Requestor Privilege-Level (RPL) Field. Bits 1–0. RPL represents the privilege level (CPL) theprocessor is operating under at the time the TSS selector is loaded into the task register.12.2.2 TSS DescriptorThe TSS descriptor is a system-segment descriptor, and it can be located only in the GDT. The formatfor an 8-byte, legacy-mode and compatibility-mode TSS descriptor can be found in “SystemDescriptors” on page 83. The format for a 16-byte, 64-bit mode TSS descriptor can be found in“System Descriptors” on page 88.The fields within a TSS descriptor (all modes) are described in “Descriptor Format” on page 77. Thefollowing additional information applies to TSS descriptors:•Segment Limit—A TSS descriptor must have a segment limit value of at least 67h, which defines aminimum TSS size of 68h (104 decimal) bytes.
If the limit is less than 67h, an invalid-TSSexception (#TS) occurs during the task switch. When an I/O-permission bitmap, interruptredirection bitmap, or additional state information is included in the TSS, the limit must be set to avalue large enough to enclose that information. In this case, if the TSS limit is not large enough to308Task Management24593—Rev. 3.13—July 2007•AMD64 Technologyhold the additional information, a #GP exception occurs when an attempt is made to access beyondthe TSS limit. No check for the larger limit is performed during the task switch.Type—Four system-descriptor types are defined as TSS types, as shown in Table 4-5 on page 83.Bit 9 is used as the descriptor busy bit (B).
This bit indicates that the task is busy when set to 1, andavailable when cleared to 0. Busy tasks are the currently running task and any previous (outer)tasks in a nested-task hierarchy. Task recursion is not supported, and a #GP exception occurs if anattempt is made to transfer control to a busy task. See “Nesting Tasks” on page 323 for additionalinformation.In long mode, the 32-bit TSS types (available and busy) are redefined as 64-bit TSS types, and only64-bit TSS descriptors can be used.
Loading the task register with an available 64-bit TSS causesthe processor to change the TSS descriptor type to indicate a busy 64-bit TSS. Because long modedoes not support task switching, the TSS-descriptor busy bit is never cleared by the processor toindicate an available 64-bit TSS.Sixteen-bit TSS types are illegal in long mode. A general-protection exception (#GP) occurs if areference is made to a 16-bit TSS.12.2.3 Task RegisterThe task register (TR) points to the TSS location in memory, defines its size, and specifies itsattributes. As with the other descriptor-table registers, the TR has two portions.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
