Volume 2 System Programming (794096), страница 83
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A set of control registers allow the selection ofevents to be monitored and a corresponding set of counter registers track the frequency ofmonitored events. These features are used to support software-performance and hardwareperformance tuning. Performance monitoring is described in “Performance Optimization” onpage 339.A given processor implementation may include additional debug capabilities that allow monitoringprogram execution and manipulation of processor state to be manipulated. These resources aretypically intended for BIOS and platform development and, if available, are described in the BIOS andKernel Developer’s Guide for AMD Athlon™ 64 and AMD Opteron™ Processors (order# 26094) forinformation specific to a particular processor.13.1Software-Debug ResourcesSoftware can program breakpoints into the debug registers, causing a #DB exception when matchesoccur on instruction-memory addresses, data-memory addresses, or I/O addresses.
The breakpointexception (#BP) is also supported to allow software to set breakpoints by placing INT3 instructions inthe instruction memory for a program. Program control is transferred to the breakpoint exception(#BP) handler when an INT3 instruction is executed.In addition to the debug features supported by the debug registers (DR0–DR7), the processor alsosupports features supported by model-specific registers (MSRs).
Together, these capabilities provide arich set of breakpoint conditions, including:Debug and Performance Resources325AMD64 Technology•••••24593—Rev. 3.13—July 2007Breakpoint On Address Match—Breakpoints occur when the address stored in a addressbreakpoint register matches the address of an instruction or data reference. Up to four addressmatch breakpoint conditions can be set by software.Single Step All Instructions—Breakpoints can be set to occur on every instruction, allowing adebugger to examine the contents of registers as a program executes.Single Step Control Transfers—Breakpoints can be set to occur on control transfers, such as calls,jumps, interrupts, and exceptions. This can allow a debugger to narrow a problem search to aspecific section of code before enabling single stepping of all instructions.Breakpoint On Any Instruction—Breakpoints can be set on any specific instruction using either theaddress-match breakpoint condition or using the INT3 instruction to force a breakpoint when theinstruction is executed.Breakpoint On Task Switch—Software forces a #DB exception to occur when a task switch isperformed to a task with the T bit in the TSS set to 1.
Debuggers can use this capability to enable ordisable debug conditions for a specific task.Problem areas can be identified rapidly using the information supplied by the debug registers whenbreakpoint conditions occur:••Special conditions that cause a #DB exception are recorded in the DR6 debug-status register,including breakpoints due to task switches and single stepping. The DR6 register also identifieswhich address-breakpoint register (DR0–DR3) caused a #DB exception due to an address match.When combined with the DR7 debug-control register settings, the cause of a #DB exception can beidentified.To assist in analyzing the instruction sequence a processor follows in reaching its current state, thesource and destination addresses of control-transfer events are saved by the processor.
Theseinclude branches (calls and jumps), interrupts, and exceptions. Debuggers can use this informationto narrow a problem search to a specific section of code before single stepping all instructions.13.1.1 Debug RegistersThe AMD64 architecture supports the legacy debug registers, DR0–DR7. These registers areexpanded to 64 bits by the AMD64 architecture. In legacy mode and in compatibility mode, only thelower 32 bits are used. In these modes, writes to a debug register fill the upper 32 bits with zeros, andreads from a debug register return only the lower 32 bits.
In 64-bit mode, all 64 bits of the debugregisters are read and written. Operand-size prefixes are ignored.The debug registers can be read and written only when the current-protection level (CPL) is 0 (mostprivileged). Attempts to read or write the registers at a lower-privilege level (CPL>0) cause a generalprotection exception (#GP).Several debug registers described below are model-specific registers (MSRs). See “Software-DebugMSRs” on page 461 for a listing of the debug-MSR numbers and their reset values. Some processorimplementations include additional MSRs used to support implementation-specific software debugfeatures. For more information on these registers and their capabilities, refer to the BIOS writer’s guidefor the implementation.326Debug and Performance Resources24593—Rev.
3.13—July 2007AMD64 TechnologyAddress-Breakpoint Registers (DR0-DR3). Figure 13-1 on page 327 shows the format of the fouraddress-breakpoint registers, DR0-DR3. Software can load a virtual (linear) address into any of thefour registers, and enable breakpoints to occur when the address matches an instruction or datareference. The MOV DRn instructions do not check that the virtual addresses loaded into DR0–DR3are in canonical form.
Breakpoint conditions are enabled using the debug-control register, DR7 (see“Debug-Control Register (DR7)” on page 329).630Breakpoint 0 64-bit Virtual (linear) Address630Breakpoint 1 64-bit Virtual (linear) Address630Breakpoint 2 64-bit Virtual (linear) Address630Breakpoint 3 64-bit Virtual (linear) AddressFigure 13-1. Address-Breakpoint Registers (DR0–DR3)Reserved Debug Registers (DR4, DR5). The DR4 and DR5 registers are reserved and should not beused by software. These registers are aliased to the DR6 and DR7 registers, respectively.
When thedebug extensions are enabled (CR4.DE=1) attempts to access these registers cause an invalid-opcodeexception (#UD).Debug-Status Register (DR6). Figure 13-2 on page 328 shows the format of the debug-statusregister, DR6. Debug status is loaded into DR6 when an enabled debug condition is encountered thatcauses a #DB exception.Debug and Performance Resources327AMD64 Technology24593—Rev.
3.13—July 20076332MBZ31Read as 1sBits63–161514131211-43210MnemonicReservedBTBSBDReservedReservedB3B2B1B0DescriptionMBZBreakpoint Task SwitchBreakpoint Single StepBreakpoint Debug Access DetectedRead as ZeroRead as 1sBreakpoint #3 Condition DetectedBreakpoint #2 Condition DetectedBreakpoint #1 Condition DetectedBreakpoint #0 Condition Detected16 15 14 13 12RB B BAT S DZ4Read as 1s3210B3B2B1B0R/WR/WR/WR/WR/WR/WR/WR/WFigure 13-2. Debug-Status Register (DR6)Bits 15:13 of the DR6 register is never cleared by the processor and must be cleared by software afterthe contents have been read.
Register fields are:••••Breakpoint-Condition Detected (B3–B0)—Bits 3–0. The processor updates these four bits onevery debug breakpoint or general-detect condition. A bit is set to 1 if the corresponding addressbreakpoint register detects an enabled breakpoint condition, as specified by the DR7 Ln, Gn, R/Wnand LENn controls, and is cleared to 0 otherwise. For example, B1 (bit 1) is set to 1 if an addressbreakpoint condition is detected by DR1.Debug-Register-Access Detected (BD)—Bit 13. The processor sets this bit to 1 if softwareaccesses any debug register (DR0–DR7) while the general-detect condition is enabled(DR7.GD=1).Single Step (BS)—Bit 14.
The processor sets this bit to 1 if the #DB exception occurs as a result ofsingle-step mode (rFLAGS.TF=1). Single-step mode has the highest-priority among debugexceptions. Other status bits within the DR6 register can be set by the processor along with the BSbit.Task-Switch (BT)—Bit 15. The processor sets this bit to 1 if the #DB exception occurred as a resultof task switch to a task with a TSS T-bit set to 1.All remaining bits in the DR6 register are reserved. Reserved bits 31–16 and 11–4 must all be set to 1,while reserved bit 12 must be cleared to 0. In 64-bit mode, the upper 32 bits of DR6 are reserved andmust be written with zeros. Writing a 1 to any of the upper 32 bits results in a general-protectionexception, #GP(0).328Debug and Performance Resources24593—Rev.
3.13—July 2007AMD64 TechnologyDebug-Control Register (DR7). Figure 13-3 on page 329 shows the format of the debug-controlregister, DR7. DR7 is used to establish the breakpoint conditions for the address-breakpoint registers(DR0–DR3) and to enable debug exceptions for each address-breakpoint register individually. DR7 isalso used to enable the general-detect breakpoint condition.6332MBZ31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7RGG L GLEN3 R/W3 LEN2 R/W2 LEN1 R/W1 LEN0 R/W0 RAZRAZ AE E 3D1Bits63–3231-3029-2827-2625-2423-2221-2019-1817-1615-141312-11109876543210MnemonicReservedLEN3R/W3LEN2R/W2LEN1R/W1LEN0R/W0ReservedGDReservedReservedGELEG3L3G2L2G1L1G0L0DescriptionMBZLength of Breakpoint #3Type of Transaction(s) to TrapLength of Breakpoint #2Type of Transaction(s) to TrapLength of Breakpoint #1Type of Transaction(s) to TrapLength of Breakpoint #0Type of Transaction(s) to TrapRead as 0sGeneral Detect EnabledRead as 0sRead as 1Global Exact Breakpoint EnabledLocal Exact Breakpoint EnabledGlobal Exact Breakpoint #3 EnabledLocal Exact Breakpoint #3 EnabledGlobal Exact Breakpoint #2 EnabledLocal Exact Breakpoint #2 EnabledGlobal Exact Breakpoint #1 EnabledLocal Exact Breakpoint #1 EnabledGlobal Exact Breakpoint #0 EnabledLocal Exact Breakpoint #0 Enabled6543210L3G2L2G1L1G0L0R/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WR/WFigure 13-3.
Debug-Control Register (DR7)The fields within the DR7 register are all read/write. These fields are:•Local-Breakpoint Enable (L3–L0)—Bits 6, 4, 2, and 0 (respectively). Software individually setsthese bits to 1 to enable debug exceptions to occur when the corresponding address-breakpointregister (DRn) detects a breakpoint condition while executing the current task. For example, if L1Debug and Performance Resources329AMD64 Technology••••••24593—Rev. 3.13—July 2007(bit 2) is set to 1 and an address-breakpoint condition is detected by DR1, a #DB exception occurs.These bits are cleared to 0 by the processor when a hardware task-switch occurs.Global-Breakpoint Enable (G3–G0)—Bits 7, 5, 3, and 1 (respectively).
Software sets these bits to1 to enable debug exceptions to occur when the corresponding address-breakpoint register (DRn)detects a breakpoint condition while executing any task. For example, if G1 (bit 3) is set to 1 and anaddress-breakpoint condition is detected by DR1, a #DB exception occurs. These bits are nevercleared to 0 by the processor.Local-Enable (LE)—Bit 8.
Software sets this bit to 1 in legacy implementations to enable exactbreakpoints while executing the current task. This bit is ignored by implementations of theAMD64 architecture. All breakpoint conditions, except certain string operations preceded by arepeat prefix, are exact.Global-Enable (GE)—Bit 9.
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