Volume 2 System Programming (794096), страница 81
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In this example, all ports from 78h and above will cause a #GP exception,as if their permission bit was set to 1.12.2.5 64-Bit Task State SegmentAlthough the hardware task-switching mechanism is not supported in long mode, a 64-bit task statesegment (TSS) must still exist. System software must create at least one 64-bit TSS for use afteractivating long mode, and it must execute the LTR instruction, in 64-bit mode, to load the TR registerwith a pointer to the 64-bit TSS that serves both 64-bit-mode programs and compatibility-modeprograms.The legacy TSS contains several fields used for saving and restoring processor-state information. Thelegacy fields include general-purpose register, EFLAGS, CR3 and segment-selector register state,among others. Those legacy fields are not supported by the 64-bit TSS.
System software must save andrestore the necessary processor-state information required by the software-multitaskingimplementation (if multitasking is supported). Figure 12-8 on page 317 shows the format of a 64-bitTSS.The 64-bit TSS holds several pieces of information important to long mode that are not directly relatedto the task-switch mechanism:•RSPn—Bytes 1Bh–04h. The full 64-bit canonical forms of the stack pointers (RSP) for privilegelevels 0 through 2.Task Management315AMD64 Technology••24593—Rev. 3.13—July 2007ISTn—Bytes 5Bh–24h.
The full 64-bit canonical forms of the interrupt-stack-table (IST) pointers.See “Interrupt-Stack Table” on page 243 for a description of the IST mechanism.I/O Map Base Address—Bytes 67h–66h. The 16-bit offset to the I/O-permission bit map from the64-bit TSS base. The function of this field is identical to that in a legacy 32-bit TSS. See “I/OPermission Bitmap” on page 314 for more information.316Task Management24593—Rev. 3.13—July 2007AMD64 TechnologyBit Offset3116 150IOPBBaseI/O-Permission Bitmap (IOPB) (Up to 8 Kbytes)↑↓ByteOffset↑↓I/O Map Base AddressReserved, IGN+64h+60hReserved, IGN+5ChIST7[63:32]+58hIST7[31:0]+54hIST6[63:32]+50hIST6[31:0]+4ChIST5[63:32]+48hIST5[31:0]+44hIST4[63:32]+40hIST4[31:0]+3ChIST3[63:32]+38hIST3[31:0]+34hIST2[63:32]+30hIST2[31:0]+2ChIST1[63:32]+28hIST1[31:0]+24h+20hReserved, IGN+1ChRSP2[63:32]+18hRSP2[31:0]+14hRSP1[63:32]+10hRSP1[31:0]+0ChRSP0[63:32]+08hRSP0[31:0]+04hReserved, IGN+00hFigure 12-8.
Long Mode TSS FormatTask Management317AMD64 Technology24593—Rev. 3.13—July 200712.2.6 Task Gate Descriptor (Legacy Mode Only)Task-gate descriptors hold a selector reference to a TSS and are used to control access between tasks.Unlike a TSS descriptor or other gate descriptors, a task gate can be located in any of the threedescriptor tables (GDT, LDT, and IDT). Figure 12-9 shows the format of a task-gate descriptor.3116 15 14 13 12 11Reserved, IGNPSType70Reserved, IGNReserved, IGNTSS SelectorFigure 12-9.DPL8+4+0Task-Gate Descriptor, Legacy Mode OnlyThe task-gate descriptor fields are:•••System (S) and Type—Bits 12 and 11–8 (respectively) of byte +4.
These bits are encoded bysoftware as 00101b to indicate a task-gate descriptor type.Present (P)—Bit 15 of byte +4. The segment-present bit indicates the segment referenced by thegate descriptor is loaded in memory. If a reference is made to a segment when P=0, a segment-notpresent exception (#NP) occurs. This bit is set and cleared by system software and is never alteredby the processor.Descriptor Privilege-Level (DPL)—Bits 14–13 of byte +4. The DPL field indicates the gatedescriptor privilege level.
DPL can be set to any value from 0 to 3, with 0 specifying the mostprivilege and 3 the least privilege.12.3Hardware Task-Management in Legacy ModeThis section describes the operation of the task-switch mechanism when the processor is running inlegacy mode. None of these features are supported in long mode (either compatibility mode or 64-bitmode).12.3.1 Task Memory-MappingThe hardware task-switch mechanism gives system software a great deal of flexibility in managing thesharing and isolation of memory—both virtual (linear) and physical—between tasks.Segmented Memory.
The segmented memory for a task consists of the segments that are loadedduring a task switch and any segments that are later accessed by the task code. The hardware taskswitch mechanism allows tasks to either share segments with other tasks, or to access segments inisolation from one another.
Tasks that share segments actually share a virtual-address (linear-address)space, but they do not necessarily share a physical-address space. When paging is enabled, the virtualto-physical mapping for each task can differ, as is described in the following section. Shared segments318Task Management24593—Rev.
3.13—July 2007AMD64 Technologydo share physical memory when paging is disabled, because virtual addresses are used as physicaladdresses.A number of options are available to system software that shares segments between tasks:•••Sharing segment descriptors using the GDT. All tasks have access to the GDT, so it is possible forsegments loaded in the GDT to be shared among tasks.Sharing segment descriptors using a single LDT. Each task has its own LDT, and that LDT selectoris automatically saved and restored in the TSS by the processor during task switches. Tasks,however, can share LDTs simply by storing the same LDT selector in multiple TSSs. Using theLDT to manage segment sharing and segment isolation provides more flexibility to systemsoftware than using the GDT for the same purpose.Copying shared segment descriptors into multiple LDTs.
Segment descriptors can be copied bysystem software into multiple LDTs that are otherwise not shared between tasks. Allowingsegment sharing at the segment-descriptor level, rather than the LDT level or GDT level, providesthe greatest flexibility to system software.In all three cases listed above, the actual data and instructions are shared between tasks only when thetasks’ virtual-to-physical address mappings are identical.Paged Memory.
Each task has its own page-translation table base-address (CR3) register, and thatregister is automatically saved and restored in the TSS by the processor during task switches. Thisallows each task to point to its own set of page-translation tables, so that each task can translate virtualaddresses to physical addresses independently. Page translation must be enabled for changes in CR3values to have an effect on virtual-to-physical address mapping.
When page translation is disabled, thetables referenced by CR3 are ignored, and virtual addresses are equivalent to physical addresses.12.3.2 Switching TasksThe hardware task-switch mechanism transfers program control to a new task when any of thefollowing occur:•••••A CALL or JMP instruction with a selector operand that references a task gate is executed.
Thetask gate can be located in either the LDT or GDT.A CALL or JMP instruction with a selector operand that references a TSS descriptor is executed.The TSS descriptor must be located in the GDT.A software-interrupt instruction (INTn) is executed that references a task gate located in the IDT.An exception or external interrupt occurs, and the vector references a task gate located in the IDT.An IRET is executed while the EFLAGS.NT bit is set to 1, indicating that a return is beingperformed from an inner-level task to an outer-level task.
The new task is referenced using theselector stored in the current-task link field. See “Nesting Tasks” on page 323 for additionalinformation. The RET instruction cannot be used to switch tasks.When a task switch occurs, the following operations are performed automatically by the processor:Task Management319AMD64 Technology••••••••24593—Rev. 3.13—July 2007The processor performs privilege-checking to determine whether the currently-executing programis allowed to access the target task. If this check fails, the task switch is aborted without modifyingthe processor state, and a general-protection exception (#GP) occurs.
The privilege checksperformed depend on the cause of the task switch:- If the task switch is initiated by a CALL or JMP instruction through a TSS descriptor, theprocessor checks that both the currently-executing program CPL and the TSS-selector RPL arenumerically less-than or equal-to the TSS-descriptor DPL.- If the task switch takes place through a task gate, the CPL and task-gate RPL are comparedwith the task-gate DPL, and no comparison is made using the TSS-descriptor DPL. See “TaskSwitches Using Task Gates” on page 321.- Software interrupts, hardware interrupts, and exceptions all transfer control without checkingthe task-gate DPL.- The IRET instruction transfers control without checking the TSS-descriptor DPL.The processor performs limit-checking on the target TSS descriptor to verify that the TSS limit isgreater than or equal to 67h (at least 104 bytes).
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