Volume 2 System Programming (794096), страница 84
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Software sets this bit to 1 in legacy implementations to enable exactbreakpoints while executing any task. This bit is ignored by implementations of the AMD64architecture. All breakpoint conditions, except certain string operations preceded by a repeatprefix, are exact.General-Detect Enable (GD)—Bit 13. Software sets this bit to 1 to cause a debug exception tooccur when an attempt is made to execute a MOV DRn instruction to any debug register(DR0–DR7). This bit is cleared to 0 by the processor when the #DB handler is entered, allowingthe handler to read and write the DRn registers. The #DB exception occurs before executing theinstruction, and DR6.BD is set by the processor.
Software debuggers can use this bit to prevent thecurrently-executing program from interfering with the debug operation.Read/Write (R/W3–R/W0)—Bits 29–28, 25–24, 21–20, and 17–16 (respectively). Software setsthese fields to control the breakpoint conditions used by the corresponding address-breakpointregisters (DRn). For example, control-field R/W1 (bits 21–20) controls the breakpoint conditionsfor the DR1 register. The R/Wn control-field encodings specify the following conditions for anaddress-breakpoint to occur:- 00—Only on instruction execution.- 01—Only on data write.- 10—This encoding is further qualified by CR4.DE as follows:. CR4.DE=0—Condition is undefined..
CR4.DE=1—Only on I/O read or I/O write.- 11—Only on data read or data write.Length (LEN3–LEN0)—Bits 31–30, 27–26, 23–22, and 19–18 (respectively). Software sets thesefields to control the range used in comparing a memory address with the corresponding addressbreakpoint register (DRn). For example, control-field LEN1 (bits 23–22) controls the breakpointcomparison range for the DR1 register.The value in DRn defines the low-end of the address range used in the comparison. LENn is usedto mask the low-order address bits in the corresponding DRn register so that they are not used inthe address comparison. To work properly, breakpoint boundaries must be aligned on an address330Debug and Performance Resources24593—Rev.
3.13—July 2007AMD64 Technologycorresponding to the range size specified by LENn. The LENn control-field encodings specify thefollowing address-breakpoint-comparison ranges:- 00—1 byte.- 01—2 byte, must be aligned on a word boundary.- 10—8 byte, must be aligned on a quadword boundary. (Long mode only; otherwise undefined.)- 11—4 byte, must be aligned on a doubleword boundary.If the R/Wn field is used to specify instruction breakpoints (R/Wn=00), the corresponding LENnfield must be set to 00. Setting LENn to any other value produces undefined results.All remaining bits in the DR7 register are reserved. Reserved bits 15–14 and 12–11 must all be clearedto 0, while reserved bit 10 must be set to 1. In 64-bit mode, the upper 32 bits of DR7 are reserved andmust be written with zeros. Writing a 1 to any of the upper 32 bits results in a general-protection#GP(0) exception.64-Bit-Mode Extended Debug Registers.
In 64-bit mode, additional encodings for debug registersare available. The REX.R bit, in a REX prefix, is used to modify the ModRM reg field when that fieldencodes a control register, as shown in “REX Prefixes” in Volume 3. These additional encodingsenable the processor to address DR8–DR15.Access to the DR8–DR15 registers is implementation-dependent.
The architecture does not requireany of these extended debug registers to be implemented. Any attempt to access an unimplementedregister results in an invalid-opcode exception (#UD).Debug-Control MSR (DebugCtlMSR). Figure 13-4 shows the format of the debug-control MSR,DebugCtlMSR. DebugCtlMSR provides additional debug controls over control-transfer recording andsingle stepping, and external-breakpoint reporting and trace messages. DebugCtlMSR is an MSR andis read and written using the RDMSR and WRMSR instructions.Debug and Performance Resources331AMD64 Technology24593—Rev.
3.13—July 20076332Reserved316ReservedBits63-6543210MnemonicReservedPB3PB2PB1PB0BTFLBRDescriptionR/WPerformance Monitoring Pin ControlPerformance Monitoring Pin ControlPerformance Monitoring Pin ControlPerformance Monitoring Pin ControlBranch Single StepLast-Branch RecordR/WR/WR/WR/WR/WR/WFigure 13-4.5PB34PB23PB12PB01 0B LT BF RDebug-Control MSR (DebugCtlMSR)The fields within the DebugCtlMSR register are:•••Last-Branch Record (LBR)—Bit 0, read/write.
Software sets this bit to 1 to cause the processor torecord the source and target addresses of the last control transfer taken before a debug exceptionoccurs. The recorded control transfers include branch instructions, interrupts, and exceptions. See“Control-Transfer Breakpoint Features” on page 338 for more details on the registers.
SeeFigure 13-5 on page 333 for the format of the control-transfer recording MSR's.Branch Single Step (BTF)—Bit 1, read/write. Software uses this bit to change the behavior of therFLAGS.TF bit. When this bit is cleared to 0, the rFLAGS.TF bit controls instruction singlestepping, (normal behavior). When this bit is set to 1, the rFLAGS.TF bit controls single steppingon control transfers. The single-stepped control transfers include branch instructions, interrupts,and exceptions. Control-transfer single stepping requires both BTF=1 and rFLAGS.TF=1.
See“Control-Transfer Breakpoint Features” on page 338 for more details on control-transfer singlestepping.Performance-Monitoring/Breakpoint Pin-Control (PBi)—Bits 5–2, read/write. Software usesthese bits to control the type of information reported by the four external performancemonitoring/breakpoint pins on the processor.
When a PBi bit is cleared to 0, the correspondingexternal pin (BPi) reports performance-monitor information. When a PBi bit is set to 1, thecorresponding external pin (BPi) reports breakpoint information.All remaining bits in the DebugCtlMSR register are reserved.Control-Transfer Recording MSRs. Figure 13-5 on page 333 shows the format of the 64-bitcontrol-transfer recording MSRs: LastBranchToIP, LastBranchFromIP, LastExceptionToIP, and332Debug and Performance Resources24593—Rev. 3.13—July 2007AMD64 TechnologyLastExceptionFromIP.
These registers are loaded automatically by the processor when theDebugCtlMSR.LBR bit is set to 1. These MSRs are read-only.630LastBranchToIP - 64-bit Segment Offset (RIP)630LastBranchFromIP - 64-bit Segment Offset (RIP)630LastExceptionToIP - 64-bit Segment Offset (RIP)630LastExceptionFromIP - 64-bit Segment Offset (RIP)Figure 13-5.13.2Control-Transfer Recording MSRsBreakpoints13.2.1 Setting BreakpointsBreakpoints can be set to occur on either instruction addresses or data addresses using the breakpointaddress registers, DR0–DR3 (DRn). The values loaded into these registers represent the breakpointlocation virtual address.
The debug-control register, DR7, is used to enable the breakpoint registersand to specify the type of access and the range of addresses that can trigger a breakpoint.Software enables the DRn registers using the corresponding local-breakpoint enable (Ln) or globalbreakpoint enable (Gn) found in the DR7 register. Ln is used to enable breakpoints only while thecurrent task is active, and it is cleared by the processor when a task switch occurs. Gn is used to enablebreakpoints for all tasks, and it is never cleared by the processor.The R/Wn fields in DR7, along with the CR4.DE bit, specify the type of access required to trigger abreakpoint when an address match occurs on the corresponding DRn register.
Breakpoints can be set tooccur on instruction execution, data reads and writes, and I/O reads and writes. The R/Wn andCR4.DE encodings used to specify the access type are described on page 330 of “Debug-ControlRegister (DR7).”The LENn fields in DR7 specify the size of the address range used in comparison with data orinstruction addresses. LENn is used to mask the low-order address bits in the corresponding DRnregister so that they are not used in the address comparison. Breakpoint boundaries must be aligned onan address corresponding to the range size specified by LENn. Assuming the access type matches thetype specified by R/Wn, a breakpoint occurs if any accessed byte falls within the range specified byDebug and Performance Resources333AMD64 Technology24593—Rev.
3.13—July 2007LENn. For instruction breakpoints, LENn must specify a single-byte range. The LENn encodings usedto specify the address range are described on page 330 of “Debug-Control Register (DR7).”Table 13-1 on page 334 shows several examples of data accesses, and whether or not they cause a #DBexception to occur based on the breakpoint address in DRn and the breakpoint-address range specifiedby LENn. In this table, R/Wn always specifies read/write access.Table 13-1.
Breakpoint-Setting ExamplesData-AccessAddress(hexadecimal)Access Size(bytes)Byte-Addresses in DataAccess(hexadecimal)Breakpoint-AddressRange(hexadecimal)ResultDRn=F000, LENn=00 (1 Byte)8EFFB, EFFC, EFFD, EFFE,EFFF, F000, F0012EFFE, EFFF4EFFE, EFFF, F000, F001F0001F000F0012F001, F002F0054F005, F006, F007, F008EFFBEFFE#DB—F000#DB—DRn=F004, LENn=11 (4 Bytes)8EFFB, EFFC, EFFD, EFFE,EFFF, F000, F0012EFFE, EFFF4EFFE, EFFF, F000, F001F0001F000F0012F001, F002F0054F005, F006, F007, F008EFFBEFFEF004–F007—#DBDRn=F005, LENn=10 (8 Bytes)8EFFB, EFFC, EFFD, EFFE,EFFF, F000, F0012EFFE, EFFF4EFFE, EFFF, F000, F001F0001F000F0012F001, F002F0054F005, F006, F007, F008EFFBEFFE#DB—F000–F007#DBNote:“—” indicates no #DB occurs.334Debug and Performance Resources24593—Rev.
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