Volume 2 System Programming (794096), страница 88
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3.13—July 2007AMD64 TechnologyCounter and Processor ID). The RDTSC and RDTSCP instructions load the contents of the TSC intothe EDX register and the EAX register. The high 32 bits are loaded into EDX, and the low 32 bits areloaded into EAX. The RDTSC and RDTSCP instructions can be executed at any privilege level andfrom any processor mode. However, system software can disable the RDTSC or RDTSCP instructionsfor programs that run at CPL > 0 by setting CR4.TSD (the time-stamp disable bit) to 1.
WhenCR4.TSD = 1 and CPL > 0, attempts to execute RDSTC or RDSTCP result in a general-protectionexception (#GP).Some implementations allow the TSC register to be read and written using the RDMSR and WRMSRinstructions, respectively. Support of this capability, however, is not required by the architecture, andsoftware should avoid using these instructions to access the TSC. The programmer should use theCPUID instruction to determine whether these features are supported. If EDX bit 4 (as returned byCPUID function 1) is set, then the processor supports TSC, the RDTSC instruction and CR4.TSD. IfEDX bit 27 returned by CPUID function 8000_0001h is set, then the processor supports the RDTSCPinstruction.The TSC register can be used by performance-analysis applications, along with the performancemonitoring registers, to help determine the relative frequency of an event or its duration.
Software canalso use the TSC to time software routines to help identify candidates for optimization. In general, theTSC should not be used to take very short time measurements, because the resulting measurement isnot guaranteed to be identical each time it is made. The RDTSC instruction (unlike the RDTSCPinstruction) is not serializing, and can be executed out-of-order with respect to other instructionsaround it. Even when bound by serializing instructions, the system environment at the time theinstruction is executed can cause additional cycles to be counted before the TSC value is loaded intoEDX:EAX.The behavior of the RDTSC (Read Time-Stamp Counter (TSC)) and RDTSCP (Read Time-StampCounter and Processor ID) is implementation dependent.
When using these instructions, programmersmust be aware that the TSC counts at a constant rate, but may be affected by power management events(such as frequency changes), depending on the processor implementation. Consult the BIOS andkernel developer’s guide for your AMD processor implementation for information concerning theeffect of power management on the TSC.Debug and Performance Resources345AMD64 Technology34624593—Rev. 3.13—July 2007Debug and Performance Resources24593—Rev. 3.13—July 200714AMD64 TechnologyProcessor Initialization and Long ModeActivationThis chapter describes the hardware actions taken following a processor reset and the steps that mustbe taken to initialize processor resources and activate long mode.
In some cases the actions requiredare implementation-specific with references made to the appropriate implementation-specificdocumentation.14.1Reset and InitializationSystem logic initializes the processor in one of two ways. One method is to assert an external resetsignal (typically designated RESET#). The other method, referred to here as INIT, is performed usingimplementation-dependent external signalling. Both initialization techniques place the processor inreal mode and initialize processor resources to a known, consistent state from which software canbegin execution. The differences between the two methods are:••RESET#—This method provides an optional built-in self test (BIST) that can be performed as partof the RESET# process.INIT—This method does not modify the following state:- Memory hierarchy, including internal and external caches.- 128-bit media, 64-bit media, or x87 resources.- Memory-type range registers (MTRRs).- Machine-check registers.Some, but not all, model-specific registers (MSRs) are modified by an INIT.BIST cannot be performed as part of the INIT process.The processor always performs RESET# after it is powered up, but RESET# can be performed at anytime.
An INIT can be performed at any time after the processor is powered up.14.1.1 Built-In Self Test (BIST)An optional built-in self-test can be performed after RESET# is asserted. The mechanism fortriggering the BIST is implementation-specific, and can be found in the hardware documentation forthe implementation. The number of processor cycles BIST can consume before completing is alsoimplementation-specific but typically consumes several million cycles.BIST can be used by system implementations to assist in verifying system integrity, thereby improvingsystem reliability, availability, and serviceability.
The internal BIST hardware generally tests allinternal array structures for errors. These structures can include (but are not limited to):••All internal caches, including the tag arrays as well as the data arrays.All TLBs.Processor Initialization and Long Mode Activation347AMD64 Technology••24593—Rev. 3.13—July 2007Internal ROMs, such as the microcode ROM and floating-point constant ROM.Branch-prediction structures.EAX is loaded with zero if BIST completes without detecting errors. If any hardware faults aredetected during BIST, a non-zero value is loaded into EAX.14.1.2 Clock Multiplier SelectionThe internal processor clock runs at some multiple of the system clock.
The processor-to-system clockmultiple does not have to be fixed by a processor implementation but instead can be programmablethrough hardware or software, or some combination of the two. For information on selecting theprocessor-clock multiplier, refer to the BIOS writer’s guide for the implementation.14.1.3 Processor Initialization StateTable 14-1 shows the initial processor state following either RESET# or INIT. Except as indicated,processor resources generally are set to the same value after either RESET# or INIT.Table 14-1. Initial Processor StateProcessor ResourceReset (RESET#) ValueInitialization (INIT) ValueCD and NW are unchangedBit 4 (reserved) = 1All others = 0CR00000_0000_6000_0010hCR2, CR3, CR40CR80RFLAGS0000_0000_0000_0002hEFER0RIP0000_0000_0000_FFF0hCSSelector = F000hBase = 0000_0000_FFFF_0000hLimit = FFFFhAttributes = See Table 14-2 on page 350DS, ES, FS, GS, SSGDTR, IDTRLDTR, TR348Not modifiedSelector = 0000hBase = 0Limit = FFFFhAttributes = See Table 14-2 on page 350Base = 0Limit = FFFFhSelector = 0000hBase = 0Limit = FFFFhAttributes = See Table 14-2 on page 350Processor Initialization and Long Mode Activation24593—Rev.
3.13—July 2007AMD64 TechnologyTable 14-1. Initial Processor State (continued)Processor ResourceReset (RESET#) ValueInitialization (INIT) ValueRAX0(non-zero if BIST is run and fails)RDXFamily/Model/Stepping, including extended family and extendedmodel—see “Processor Implementation Information” on page 3510RBX, RCX, RBP, RSP, RDI, RSI,R8, R9, R10, R11, R12, R13, R14, 0R15x87 Floating-Point StateFPR0–FPR7 = 0Control Word = 0040hStatus Word = 0000hTag Word = 5555hInstruction CS = 0000hInstruction Offset = 0x87 Instruction Opcode = 0Data-Operand DS = 0000hData-Operand Offset = 0Not modified64-Bit Media StateMMX0–MMX7 = 0Not modified128-Bit Media StateXMM0–XMM15 = 0MXCSR = 1F80hNot modifiedMemory-Type Range RegistersSee “Memory-Typing MSRs” onpage 458Not modifiedMachine-Check RegistersSee “Machine-Check MSRs” onpage 459Not modifiedDR0, DR1, DR2, DR30DR60000_0000_FFFF_0FF0hDR70000_0000_0000_0400hTime-Stamp Counter0Not modifiedPerformance-Monitor ResourcesSee “Performance-MonitoringMSRs” on page 461Not modifiedOther Model-Specific RegistersSee “MSR Cross-Reference” onpage 453Not modifiedInvalidatedNot modifiedEnabledNot modifiedInstruction and Data CachesInstruction and Data TLBsAPICSMRAM Base Address (SMBASE) 0003_0000hNot modifiedTable 14-2 on page 350 shows the initial state of the segment-register attributes (located in the hiddenportion of the segment registers) following either RESET# or INIT.Processor Initialization and Long Mode Activation349AMD64 Technology24593—Rev.
3.13—July 2007Table 14-2. Initial State of Segment-Register AttributesValue(Binary)AttributeDescriptionG0Byte GranularityD/B016-Bit SegmentL (CS Only)0Legacy-Mode SegmentP1Segment is PresentDPL00Privilege-Level 0CodeSegmentS=1Type = 1010Executable/Readable Code SegmentDataSegmentS=1Type = 0010Read/Write Data SegmentLDTRS=0Type = 0010LDTTRS=0Type = 0011Busy 16-Bit TSSS andType14.1.4 Multiple Processor InitializationFollowing reset in multiprocessor configurations, the processors use a multiple-processor initializationprotocol to negotiate which processor becomes the bootstrap processor. This bootstrap processor thenexecutes the system initialization code while the remaining processors wait for software initializationto complete.
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