Volume 2 System Programming (794096), страница 89
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For further information, see the documentation for particular implementations of thearchitecture.14.1.5 Fetching the First InstructionAfter a RESET# or INIT, the processor is operating in 16-bit real mode. Normally within real mode,the code-segment base-address is formed by shifting the CS-selector value left four bits.
The baseaddress is then added to the value in EIP to form the physical address into memory. As a result, theprocessor can only address the first 1 Mbyte of memory when in real mode.However, immediately following RESET# or INIT, the CS-selector register is loaded with F000h, butthe CS base-address is not formed by left-shifting the selector. Instead, the CS base-address isinitialized to FFFF_0000h. EIP is initialized to FFF0h. Therefore, the first instruction fetched frommemory is located at physical-address FFFF_FFF0h (FFFF_0000h + 0000_FFF0h).The CS base-address remains at this initial value until the CS-selector register is loaded by software.This can occur as a result of executing a far jump instruction or call instruction, for example.
When CSis loaded by software, the new base-address value is established as defined for real mode (by leftshifting the selector value four bits).350Processor Initialization and Long Mode Activation24593—Rev. 3.13—July 200714.2AMD64 TechnologyHardware Configuration14.2.1 Processor Implementation InformationSoftware can read processor-identification information from the EDX register immediately followingRESET# or INIT. This information can be used to initialize software to perform processor-specificfunctions.
The information stored in EDX is defined as follows:•••Stepping ID (bits 3–0)—This field identifies the processor-revision level.Extended Model (bits 19–16) and Model (bits 7–4)—These fields combine to differentiateprocessor models within a instruction family. For example, two processors may share the samemicroarchitecture but differ in their feature set. Such processors are considered different modelswithin the same instruction family. This is a split field, comprising an extended-model portion inbits 19–16 with a legacy portion in bits 7–4Extended Family (bits 27–20) and Family (bits 11–8)—These fields combine to differentiateprocessors by their microarchitecture.The CPUID instruction can be used to obtain the same information. This is done by executing CPUIDwith either function 1 or function 8000_0001h.
Additional information about the processor and thefeatures supported can be gathered using CPUID with other feature codes. See “Processor FeatureIdentification” on page 61 for additional information.14.2.2 Enabling Internal CachesFollowing a RESET# (but not an INIT), all instruction and data caches are disabled, and their contentsare invalidated (the MOESI state is set to the invalid state). Software can enable these caches byclearing the cache-disable bit (CR0.CD) to zero (RESET# sets this bit to 1). Software can furtherrefine caching based on individual pages and memory regions. Refer to “Cache Control Mechanisms”on page 177 for more information on cache control.Memory-Type Range Registers (MTRRs).
F o l l ow i n g a R E S E T # ( b u t n o t a n I N I T ) , t h eMTRRdefType register is cleared to 0, which disables the MTRR mechanism. The variable-range andfixed-range MTRR registers are not initialized and are therefore in an undefined state. Before enablingthe MTRR mechanism, the initialization software (usually BIOS) must load these registers with aknown value to prevent unexpected results. Clearing these registers, for example, sets memory to theuncacheable (UC) type.14.2.3 Initializing Media and x87 Processor StateSome resources used by x87 floating-point instructions and 128-bit media instructions must beinitialized by software before being used. Initialization software can use the CPUID instruction todetermine whether the processor supports these instructions, and then initialize their resources asappropriate.x87 Floating-Point State Initialization.
Table 14-3 on page 352 shows the differences between theinitial x87 floating-point state following a RESET# and the state established by the FINIT/FNINITProcessor Initialization and Long Mode Activation351AMD64 Technology24593—Rev. 3.13—July 2007instruction. An INIT does not modify the x87 floating-point state. The initialization software canexecute an FINIT or FNINIT instruction to prepare the x87 floating-point unit for use by applicationsoftware. The FINIT and FNINIT instructions have no effect on the 64-bit media state.Table 14-3. x87 Floating-Point State Initializationx87 Floating-PointResourceRESET#FINIT/FNINITInstructionsFPR0–FPR70Not modifiedControl Word0040h• Round to nearest• Single precision• Unmask all exceptions037Fh• Round to nearest• Extended precision• Mask all exceptionsStatus Word0000hTag Word5555h (FPRn contain zero) FFFFh (FPRn are empty)Instruction CS0000hInstruction Offset0x87 InstructionOpcode0Data-Operand DS0000hData-Operand Offset0Initialization software should also load the MP, EM, and NE bits in the CR0 register as appropriate forthe operating system.
The recommended settings for implementations of the AMD64 architecture are:•••MP=1—Setting MP to 1 causes a device-not-available exception (#NM) to occur when theFWAIT/WAIT instruction is executed and the task-switched bit (CR0.TS) is set to 1. This supportsoperating systems that perform lazy context-switching of x87 floating-point state.EM=0—Clearing EM to 0 allows the x87 floating-point unit to execute instructions rather thancausing a #NM exception (CR0.EM=1). System software sets EM to 1 only when softwareemulation of x87 instructions is desired.NE=1—Setting NE to 1 causes x87 floating-point exceptions to be handled by the floating-pointexception-pending exception (#MF) handler. Clearing this bit causes the processor to externallyindicate the exception occurred, and an external device can then cause an external interrupt tooccur in response.Refer to “CR0 Register” on page 42 for additional information on these control bits.64-Bit Media State Initialization.
There are no special requirements placed on software to initializethe processor state used by 64-bit media instructions. This state is initialized completely by theprocessor following a RESET#. System software should leave CR0.EM cleared to 0 to allow executionof the 64-bit media instructions. If CR0.EM is set to 1, attempted execution of the 64-bit mediainstructions causes an invalid-opcode exception (#UD).352Processor Initialization and Long Mode Activation24593—Rev.
3.13—July 2007AMD64 TechnologyThe 64-bit media state is not modified by an INIT.128-Bit Media State Initialization. BIOS or system software must also prepare the processor toallow execution of 128-bit media instructions. The required preparations include:••••Leaving CR0.EM cleared to 0 to allow execution of the 128-bit media instructions.
If CR0.EM isset to 1, attempted execution of the 128-bit media instructions causes an invalid-opcode exception(#UD).Enabling the 128-bit media instructions by setting CR4.OSFXSR to 1. Software cannot execute the128-bit media instructions unless this bit is set. Setting this bit also indicates that system softwareuses the FXSAVE and FXRSTOR instructions to save and restore, respectively, the 128-bit mediastate.
These instructions also save and restore the 64-bit media state and x87 floating-point state.Indicating that system software uses the SIMD floating-point exception (#XF) for handling 128-bitmedia floating-point exceptions. This is done by setting CR4.OSXMMEXCPT to 1.Setting (optionally) the MXCSR mask bits to mask or unmask 128-bit media floating-pointexceptions as desired. Because this register can be read and written by application software, it isnot absolutely necessary for system software to initialize it.Refer to “CR4 Register” on page 47 for additional information on these CR4 control bits.14.2.4 Model-Specific InitializationImplementations of the AMD64 architecture can contain model-specific features and registers that arenot initialized by the processor and therefore require system-software initialization.
System softwaremust use the CPUID instruction to determine which features are supported. Model-specific featuresare generally configured using model-specific registers (MSRs), which can be read and written usingthe RDMSR and WRMSR instructions, respectively.Some of the model-specific features are pervasive across many processor implementations of theAMD64 architecture and are therefore described within this volume.
These include:•••••System-call extensions, which must be enabled in the EFER register before using the SYSCALLand SYSRET instructions. See “System-Call Extension (SCE) Bit” on page 55 for information onenabling these instructions.Memory-typing MSRs. See “Memory-Type Range Registers (MTRRs)” on page 351 forinformation on initializing and using these registers.The machine-check mechanism. See “Initializing the Machine-Check Mechanism” on page 265for information on enabling and using this capability.Extensions to the debug mechanism. See “Software-Debug Resources” on page 325 forinformation on initializing and using these extensions.The performance-monitoring resources.
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