Volume 2 System Programming (794096), страница 90
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See “Performance Optimization” on page 339 forinformation on initializing and using these resources.Initialization of other model-specific features used by the page-translation mechanism and long modeare described throughout the remainder of this section.Processor Initialization and Long Mode Activation353AMD64 Technology24593—Rev. 3.13—July 2007Some model-specific features are not pervasive across processor implementations and are thereforenot described in this volume.
For more information on these features and their initializationrequirements, refer to the BIOS writer’s guide for the implementation.14.3Initializing Real ModeA basic real-mode (real-address-mode) operating environment must be initialized so that systemsoftware can initialize the protected-mode operating environment. This real-mode environment mustinclude:••••A real-mode IDT for vectoring interrupts and exceptions to the appropriate handlers while in realmode.
The IDT base-address value in the IDTR initialized by the processor can be used, or systemsoftware can relocate the IDT by loading a new base-address into the IDTR.The real-mode interrupt and exception handlers. These must be loaded before enabling externalinterrupts.Because the processor can always accept a non-maskable interrupt (NMI), it is possible an NMIcan occur before initializing the IDT or the NMI handler.
System hardware must provide amechanism for disabling NMIs to allow time for the IDT and NMI handler to be properlyinitialized. Alternatively, the IDT and NMI handler can be stored in non-volatile memory that isreferenced by the initial values loaded into the IDTR.Maskable interrupts can be enabled by setting EFLAGS.IF after the real-mode IDT and interrupthandlers are initialized.A valid stack pointer (SS:SP) to be used by the interrupt mechanism should interrupts orexceptions occur. The values of SS:SP initialized by the processor can be used.One or more data-segment selectors for storing the protected-mode data structures that are createdin real mode.Once the real-mode environment is established, software can begin initializing the protected-modeenvironment.14.4Initializing Protected ModeProtected mode must be entered before activating long mode.
A minimal protected-mode environmentmust be established to allow long-mode initialization to take place. This environment must include thefollowing:•••A protected-mode IDT for vectoring interrupts and exceptions to the appropriate handlers while inprotected mode.The protected-mode interrupt and exception handlers referenced by the IDT. Gate descriptors foreach handler must be loaded in the IDT.A GDT which contains:- A code descriptor for the code segment that is executed in protected mode.354Processor Initialization and Long Mode Activation24593—Rev.
3.13—July 2007-AMD64 TechnologyA read/write data segment that can be used as a protected-mode stack. This stack can be usedby the interrupt mechanism if interrupts or exceptions occur.Software can optionally load the GDT with one or more data segment descriptors, a TSS descriptor,and an LDT descriptor for use by long-mode initialization software.After the protected-mode data structures are initialized, system software must load the IDTR andGDTR (and optionally, the LDTR and TR) with pointers to those data structures. Once these registersare initialized, protected mode can be enabled by setting CR0.PE to 1.If legacy paging is used during the long-mode initialization process, the page-translation tables mustbe initialized before enabling paging. At a minimum, one page directory and one page table arerequired to support page translation.
The CR3 register must be loaded with the starting physicaladdress of the highest-level table supported in the page-translation hierarchy. After these structures areinitialized and protected mode is enabled, paging can be enabled by setting CR0.PG to 1.14.5Initializing Long ModeFrom protected mode, system software can initialize the data structures required by long mode andstore them anywhere in the first 4 Gbytes of physical memory. These data structures can be relocatedabove 4 Gbytes once long mode is activated. The data structures required by long mode include thefollowing:•••An IDT with 64-bit interrupt-gate descriptors. Long-mode interrupts are always taken in 64-bitmode, and the 64-bit gate descriptors are used to transfer control to interrupt handlers running in64-bit mode. See “Long-Mode Interrupt Control Transfers” on page 239 for more information.The 64-bit mode interrupt and exception handlers to be used in 64-bit mode.
Gate descriptors foreach handler must be loaded in the 64-bit IDT.A GDT containing segment descriptors for software running in 64-bit mode and compatibilitymode, including:- Any LDT descriptors required by the operating system or application software.- A TSS descriptor for the single 64-bit TSS required by long mode.- Code descriptors for the code segments that are executed in long mode.
The code-segmentdescriptors are used to specify whether the processor is operating in 64-bit mode orcompatibility mode. See “Code-Segment Descriptors” on page 86, “Long (L) Attribute Bit” onpage 87, and “CS Register” on page 69 for more information.- Data-segment descriptors for software running in compatibility mode. The DS, ES, and SSsegments are ignored in 64-bit mode.
See “Data-Segment Descriptors” on page 87 for moreinformation.- FS and GS data-segment descriptors for 64-bit mode, if required by the operating system. Ifthese segments are used in 64-bit mode, system software can also initialize the full 64-bit baseaddresses using the WRMSR instruction. See “FS and GS Registers in 64-Bit Mode” onpage 70 for more information.Processor Initialization and Long Mode Activation355AMD64 Technology••24593—Rev. 3.13—July 2007The existing protected-mode GDT can be used to hold the long-mode descriptors described above.A single 64-bit TSS for holding the privilege-level 0, 1, and 2 stack pointers, the interrupt-stacktable pointers, and the I/O-redirection-bitmap base address (if required).
This is the only TSSrequired, because hardware task-switching is not supported in long mode. See “64-Bit Task StateSegment” on page 315 for more information.The 4-level page-translation tables required by long mode. Long mode also requires the use ofphysical-address extensions (PAE) to support physical-address sizes greater than 32 bits. See“Long-Mode Page Translation” on page 128 for more information.If paging is enabled during the initialization process, it must be disabled before enabling long mode.After the long-mode data structures are initialized, and paging is disabled, software can enable andactivate long mode.14.6Enabling and Activating Long ModeLong mode is enabled by setting the long-mode enable control bit (EFER.LME) to 1.
However, longmode is not activated until software also enables paging. When software enables paging while longmode is enabled, the processor activates long mode, which the processor indicates by setting the longmode-active status bit (EFER.LMA) to 1. The processor behaves as a 32-bit x86 processor in allrespects until long mode is activated, even if long mode is enabled. None of the new 64-bit data sizes,addressing, or system aspects available in long mode can be used until EFER.LMA=1.Table 14-4 shows the control-bit settings for enabling and activating the various operating modes ofthe AMD64 architecture.
The default address and data sizes are shown for each mode. For the methodsof overriding these default address and data sizes, see “Instruction Prefixes” in Volume 3.Table 14-4. Processor Operating ModesCompatibilityModeLegacy ModeCS.DLongMode64-BitModeCS.LModeEFER.LMA1EncodingDefaultAddressSize(bits)2DefaultDataSize(bits)210643213232016161323201616100xNote:1. EFER.LMA is set by the processor when software sets EFER.LME and CR0.PGaccording to the sequence described in “Activating Long Mode” on page 357.2. See “Instruction Prefixes” in Volume 1 for overrides to default sizes.356Processor Initialization and Long Mode Activation24593—Rev. 3.13—July 2007AMD64 TechnologyLong mode uses two code-segment-descriptor bits, CS.L and CS.D, to control the operatingsubmodes.
If long mode is active, CS.L = 1, and CS.D = 0, the processor is running in 64-bit mode, asshown in Table 14-4 on page 356. With this encoding (CS.L=1, CS.D=0), default operand size is 32bits and default address size is 64 bits. Using instruction prefixes, the default operand size can beoverridden to 64 bits or 16 bits, and the default address size can be overridden to 32 bits.The final encoding of CS.L and CS.D in long mode (CS.L=1, CS.D=1) is reserved for future use.When long mode is active and CS.L is cleared to 0, the processor is in compatibility mode, as shown inTable 14-4 on page 356.
In compatibility mode, CS.D controls default operand and address sizesexactly as it does in the legacy x86 architecture. Setting CS.D to 1 specifies default operand andaddress sizes as 32 bits. Clearing CS.D to 0 specifies default operand and address sizes as 16 bits.14.6.1 Activating Long ModeSwitching the processor to long mode requires several steps. In general, the sequence involvesdisabling paging (CR0.PG=0), enabling physical-address extensions (CR4.PAE=1), loading CR3,enabling long mode (EFER.LME=1), and finally enabling paging (CR0.PG=1).Specifically, software must follow this sequence to activate long mode:1. If starting from page-enabled protected mode, disable paging by clearing CR0.PG to 0. Thisrequires that the MOV CR0 instruction used to disable paging be located in an identity-mappedpage (virtual address equals physical address).2.
In any order:- Enable physical-address extensions by setting CR4.PAE to 1. Long mode requires the use ofphysical-address extensions (PAE) in order to support physical-address sizes greater than 32bits. Physical-address extensions must be enabled before enabling paging.- Load CR3 with the physical base-address of the level-4 page-map-table (PML4). See “LongMode Page Translation” on page 128 for details on creating the 4-level page translation tablesrequired by long mode.- Enable long mode by setting EFER.LME to 1.3. Enable paging by setting CR0.PG to 1.
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