Volume 2 System Programming (794096), страница 78
Текст из файла (страница 78)
The state of all MMX/FPR registers is saved, as well as all other x87state (the control word register, status word register, tag word, instruction pointer, data pointer, and lastopcode). After saving this state, the tag state for all MMX/FPR registers is changed to empty and isthus available for a new procedure.Starting on page 295, Figure 11-4 through Figure 11-7 show the memory formats used by theFSAVE/FNSAVE and FRSTOR instructions when storing the x87 state in various processor modesand using various effective-operand sizes.
This state includes:••x87 Data Registers- FPR0–FPR7 80-bit physical data registers.x87 Environment- FCW: x87 control word register- FSW: x87 status word register- FTW: x87 tag word- Last x87 instruction pointer- Last x87 data pointer- Last x87 opcodeThe eight data registers are stored in the 80 bytes following the environment information.
Instead ofstoring these registers in their physical order (FPR0–FPR7), the processor stores the registers in thetheir stack order, ST(0)–ST(7), beginning with the top-of-stack, ST(0).294128-Bit, 64-Bit, and x87 Programming24593—Rev. 3.13—July 2007AMD64 TechnologyBit Offset3116150ST(7)(79–48)+68h……ST(1)(15–0)ST(0)(79–64)…ST(0)(63–32)…ST(0)(31–0)+1ChData DS Selector(15–0)Reserved, IGNData Offset(31–0)00000bByteOffset+18h+14hInstruction Opcode(10–0)Instruction CS Selector(15–0)Instruction Offset(31–0)+10h+0ChReserved, IGNx87 Tag Word (FTW)+08hReserved, IGNx87 Status Word (FSW)+04hReserved, IGNx87 Control Word (FCW)+00hFigure 11-4.FSAVE/FNSAVE Image (32-Bit, Protected Mode)128-Bit, 64-Bit, and x87 Programming295AMD64 Technology24593—Rev.
3.13—July 2007Bit Offset3116150ST(7)(79–48)+68h……ST(1)(15–0)0000bST(0)(79–64)…ST(0)(63–32)…ST(0)(31–0)+1ChData Offset(31–16)0000 0000 0000bData Offset(15–0)Reserved, IGN0000bByteOffsetInstruction Offset(31–16)0Instruction Opcode(10–0)+18h+14h+10hReserved, IGNInstruction Offset(15–0)+0ChReserved, IGNx87 Tag Word (FTW)+08hReserved, IGNx87 Status Word (FSW)+04hReserved, IGNx87 Control Word (FCW)+00hFigure 11-5.
FSAVE/FNSAVE Image (32-Bit, Real/Virtual-8086 Modes)296128-Bit, 64-Bit, and x87 Programming24593—Rev. 3.13—July 2007AMD64 TechnologyBit Offset3116150ST(7)(79–64)Not Part of x87 StateByteOffset+5Ch……ST(0)(79–48)+14hST(0)(47–16)+10hST(0)(15–0)Data DS Selector(15–0)+0ChData Offset(15–0)Instruction CS Selector(15–0)+08hInstruction Offset(15–0)x87 Tag Word (FTW)+04hx87 Status Word (FSW)x87 Control Word (FCW)+00hFigure 11-6.FSAVE/FNSAVE Image (16-Bit, Protected Mode)128-Bit, 64-Bit, and x87 Programming297AMD64 Technology24593—Rev. 3.13—July 2007Bit Offset3116150ST(7)(79–64)Not Part of x87 StateST(0)(15–0)Data Offset (15–0)ByteOffset+5Ch……ST(0)(79–48)+14hST(0)(47–16)+10hData(19–16)0000 0000 0000bInstruc.0(19–16)Instruction Opcode(10–0)+0Ch+08hInstruction Offset (15–0)x87 Tag Word (FTW)+04hx87 Status Word (FSW)x87 Control Word (FCW)+00hFigure 11-7.
FSAVE/FNSAVE Image (16-Bit, Real/Virtual-8086 Modes)FLDENV/FNLDENV and FSTENV Instructions. T h e F L D E N V / F N L D E N V a n d F S T E N Vinstructions load and store only the x87 floating-point environment. These instructions, unlike theFSAVE/FNSAVE and FRSTOR instructions, do not save or restore the x87 data registers. TheFLDENV/FSTENV instructions do not save the full 64-bit data and instruction pointers. 64-bitapplications should use FXSAVE/FXRSTOR, rather than FLDENV/FSTENV. The format of the savedx87 environment images for protected mode and real/virtual mode are the same as those of the first 14bytes of the FSAVE/FNSAVE images for 16-bit operands or 32/64-bit operands, respectively.
Seefigures Figure 11-4 on page 295, Figure 11-5 on page 296, Figure 11-6 on page 297, and Figure 11-7on page 298.FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR instructions save and restorethe entire 128-bit media, 64-bit media, and x87 state. These instructions usually execute faster thanFSAVE/FNSAVE and FRSTOR because they do not normally save and restore the x87 exceptionpointers (last-instruction pointer, last data-operand pointer, and last opcode). The only case in which298128-Bit, 64-Bit, and x87 Programming24593—Rev. 3.13—July 2007AMD64 Technologythey do save the exception pointers is the relatively rare case in which the exception-summary bit in thex87 status word (FSW.ES) is set to 1, indicating that an unmasked exception has occurred. TheFXSAVE and FXRSTOR memory format contains fields for storing these values.Unlike FSAVE and FNSAVE, the FXSAVE instruction does not alter the x87 tag word.
Therefore, thecontents of the shared 64-bit MMX and 80-bit FPR registers can remain valid after an FXSAVEinstruction (or any other value the tag bits indicated before the save). Also, FXSAVE (like FNSAVE)does not check for pending unmasked-x87 floating-point exceptions.Figure 11-8 on page 300 shows the memory format of the media x87 state in long mode. When in 64bit mode using a 64-bit operand size, the format shown in Figure 11-8 is used. If a 32-bit operand sizeis used (in 64-bit mode), the memory format is the same, except that RIP and RDS are stored assel:offset pointers, as shown in Figure 11-9 on page 301.128-Bit, 64-Bit, and x87 Programming299AMD64 TechnologyFED24593—Rev. 3.13—July 2007CBA9876543210ByteReserved, IGN+1F0h……Reserved, IGN+1A0hXMM15+190hXMM14+180hXMM13+170hXMM12+160hXMM11+150hXMM10+140hXMM9+130hXMM8+120hXMM7+110hXMM6+100hXMM5+F0hXMM4+E0hXMM3+D0hXMM2+C0hXMM1+B0hXMM0+A0hReserved, IGNST(7)+90hReserved, IGNST(6)+80hReserved, IGNST(5)+70hReserved, IGNST(4)+60hReserved, IGNST(3)+50hReserved, IGNST(2)+40hReserved, IGNST(1)+30hReserved, IGNST(0)+20hMXCSR_MASKRDP1MXCSRRIP1FOP0FTW+10hFSWFCW+00h1.
Stored as sel:offset if operand size is 32 bits. 32bit sel:offset format of the pointers is shown in figure 11-9.Figure 11-8.300FXSAVE and FXRSTOR Image (64-bit Mode)128-Bit, 64-Bit, and x87 Programming24593—Rev. 3.13—July 2007FEDCA9876543210ByteReserved, IGN+1F0h……Reserved, IGN+120hXMM7+110hXMM6+100hXMM5+F0hXMM4+E0hXMM3+D0hXMM2+C0hXMM1+B0hXMM0+A0hReserved, IGNST(7)+90hReserved, IGNST(6)+80hReserved, IGNST(5)+70hReserved, IGNST(4)+60hReserved, IGNST(3)+50hReserved, IGNST(2)+40hReserved, IGNST(1)+30hReserved, IGNST(0)+20hMXCSR_MASKrsrvd, IGNBAMD64 TechnologyCSMXCSRrsrvd, IGNEIPFOPDS0FTWDPFSW+10hFCW+00hFigure 11-9.
FXSAVE and FXRSTOR Image (Non-64-bit Mode)Software can read and write all fields within the FXSAVE and FXRSTOR memory image. These fieldsinclude:•••FCW—Bytes 01h–00h. x87 control word.FSW—Bytes 03h–02h. x87 status word.FTW—Byte 04h.
x87 tag word. See “FXSAVE Format for x87 Tag Word” on page 302 foradditional information on the FTW format saved by the FXSAVE instruction.•••(Byte 05h contains the value 00h.)FOP—Bytes 07h–06h. last x87 opcode.Last x87 Instruction Pointer—A pointer to the last non-control x87 floating-point instructionexecuted by the processor:128-Bit, 64-Bit, and x87 Programming301AMD64 Technology•••••24593—Rev. 3.13—July 2007RIP (64-bit format)—Bytes 0Fh–08h.
64-bit offset into the code segment (used without a CSselector).EIP (32-bit format)—Bytes 0Bh–08h. 32-bit offset into the code segment.- CS (32-bit format)—Bytes 0Dh–0Ch. Segment selector portion of the pointer.Last x87 Data Pointer—If the last non-control x87 floating point instruction referenced memory,this value is a pointer to the data operand referenced by the last non-control x87 floating-pointinstruction executed by the processor:- RDP (64-bit format)—Bytes 17h–10h. 64-bit offset into the data segment (used without a DSselector).- DP (32-bit format)—Bytes 13h–10h.
32-bit offset into the data segment.- DS (32-bit format)—Bytes 15h–14h. Segment selector portion of the pointer.If the last non-control x87 instruction did not reference memory, then the value in the pointer isimplementation dependent.MXCSR—Bytes 1Bh–18h. 128-bit media-instruction control and status register. This register issaved only if CR4.OSFXSR is set to 1.MXCSR_MASK—Bytes 1Fh–1Ch. Set bits in MXCSR_MASK indicate supported feature bits inMXCSR. For example, if bit 6 (the DAZ bit) in the returned MXCSR_MASK field is set to 1, theDAZ mode and the DAZ flag in MXCSR are supported.
Cleared bits in MXCSR_MASK indicatereserved bits in MXCSR. If software attempts to set a reserved bit in the MXCSR register, a #GPexception will occur. To avoid this exception, after software clears the FXSAVE memory imageand executes the FXSAVE instruction, software should use the value returned by the processor inthe MXCSR_MASK field when writing a value to the MXCSR register, as follows:- MXCSR_MASK = 0: If the processor writes a zero value into the MXCSR_MASK field, thedenormals-are-zeros (DAZ) mode and the DAZ flag in MXCSR are not supported. Softwareshould use the default mask value, 0000_FFBFh (bit 6, the DAZ bit, and bits 31–16 cleared to0), to mask any value it writes to the MXCSR register to ensure that all reserved bits inMXCSR are written with 0, thus avoiding a #GP exception.- MXCSR_MASK ≠ 0: If the processor writes a non-zero value into the MXCSR_MASK field,software should AND this value with any value it writes to the MXCSR register.MMXn/FPRn—Bytes 9Fh–20h.
Shared 64-bit media and x87 floating-point registers. As in thecase of the x87 FSAVE instruction, these registers are stored in stack order ST(0)–ST(7). Theupper six bytes in the memory image for each register are reserved.XMMn—Bytes 11Fh–A0h. 128-bit media registers. These registers are saved only ifCR4.OSFXSR is set to 1.FXSAVE Format for x87 Tag Word. Rather than saving the entire x87 tag word, FXSAVE saves asingle-byte encoded version.
FXSAVE encodes each of the eight two-bit fields in the x87 tag word asfollows:•Two-bit values of 00, 01, and 10 are encoded as a 1, indicating the corresponding x87 FPRnregister holds a value.302128-Bit, 64-Bit, and x87 Programming24593—Rev. 3.13—July 2007•AMD64 TechnologyA two-bit value of 11 is encoded as a 0, indicating the corresponding x87 FPRn is empty.For example, assume an FSAVE instruction saves an x87 tag word with the value 83F1h. This tagword value describes the x87 FPRn contents as follows:x87 RegisterFPR7Tag Word Value (hex)FPR6FPR58FPR4FPR33FPR2FPR1FFPR01Tag Value (binary)1000001111110001MeaningSpecialValidValidEmptyEmptyEmptyValidZeroWhen an FXSAVE is used to write the x87 tag word to memory, it encodes the value as E3h. Thisencoded version describes the x87 FPRn contents as follows:x87 RegisterFPR7FPR6Encoded Tag Byte(hex)FPR5FPR4FPR3FPR2EFPR1FPR03Tag Value (binary)11100011MeaningValidValidValidEmptyEmptyEmptyValidValidIf necessary, software can decode the single-bit FXSAVE tag-word fields into the two-bit field FSAVEuses by examining the contents of the corresponding FPR registers saved by FXSAVE.
Table 11-1 onpage 304 shows how the FPR contents are used to find the equivalent FSAVE tag-field value. Thefraction column refers to fraction portion of the extended-precision significand (bits 62–0). Theinteger bit column refers to the integer-portion of the significand (bit 63). See “x87 Floating-PointProgramming” in Volume 1 for more information on floating-point numbering formats.128-Bit, 64-Bit, and x87 Programming303AMD64 Technology24593—Rev. 3.13—July 2007Table 11-1.
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