Volume 2 System Programming (794096), страница 76
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The size of this fieldis one byte, as compared with two bytes in previous versions of SMM.When entering SMM, the processor loads the auto-halt restart entry to indicate whether SMM wasentered from the halt state, as follows:••Bit 0 indicates the processor state upon entering SMM:- When set to 1, the processor entered SMM from the halt state.- When cleared to 0, the processor did not enter SMM from the halt state.Bits 7–1 are cleared to 0.282System-Management Mode24593—Rev. 3.13—July 2007AMD64 TechnologyThe SMM handler can write the auto-halt restart entry to specify whether the return from SMM shouldtake the processor back to the halt state or to the instruction-execution state specified by the SMMstate-save area.
The values written are:••Clear to 00h—The processor returns to the state specified by the SMM state-save area.Set to any non-zero value—The processor returns to the halt state.If the return from SMM takes the processor back to the halt state, the HLT instruction is not reexecuted. However, the halt special bus-cycle is driven on the processor bus after the RSM instructionexecutes.The result of entering SMM from a non-halt state and returning to a halt state is not predictable.10.3.8 I/O Instruction RestartThe I/O-instruction restart entry is located at offset FEC8h in the SMM state-save area. The size of thisfield is one byte, as compared with two bytes in previous versions of SMM.
The I/O-instruction restartmechanism is supported when the I/O-instruction restart bit (bit 16) in the SMM-revision identifier isset to 1. This bit is always set to 1 in the AMD64 architecture.When an I/O instruction is interrupted by an SMI, the I/O-instruction restart entry specifies whetherthe interrupted I/O instruction should be re-executed following an RSM that returns from SMM. Reexecuting a trapped I/O instruction is useful, for example, when an I/O write is performed to apowered-down disk drive. When this occurs, the system logic monitoring the access can issue an SMIto have the SMM handler power-up the disk drive and retry the I/O write.
The SMM handler does thisby querying system logic and detecting the failed I/O write, asking system logic to initiate the diskdrive power-up sequence, enabling the I/O instruction restart mechanism, and returning from SMM.Upon returning from SMM, the I/O write to the disk drive is restarted.When an SMI occurs, the processor always clears the I/O-instruction restart entry to 0. If the SMIinterrupted an I/O instruction, then the SMM handler can modify the I/O-instruction restart entry asfollows:••Clear to 00h (default value)—The I/O instruction is not restarted, and the instruction following theinterrupted I/O-instruction is executed.
When a REP (repeat) prefix is used with an I/O instruction,it is possible that the next instruction to be executed is the next I/O instruction in the repeat loop.Set to any non-zero value—The I/O instruction is restarted.While in SMM, the handler must determine the cause of the SMI and examine the processor state at thetime the SMI occurred to determine whether or not an I/O instruction was interrupted.Implementations provide state information in the SMM save-state area to assist in this determination:••••I/O Instruction Restart DWORD—indicates whether the SMI interrupted an I/O instruction, andsaves extra information describing the I/O instruction.I/O Instruction Restart RIP—the RIP of the interrupted I/O instruction.I/O Instruction Restart RCX—the RCX of the interrupted I/O instruction.I/O Instruction Restart RSI—the RSI of the interrupted I/O instruction.System-Management Mode283AMD64 Technology24593—Rev.
3.13—July 2007I/O Instruction Restart RDI—the RDI of the interrupted I/O instruction.•311615PORTFigure 10-6.7Reserved654321S SZ Z32 16SZ8REPSTRVAL0TYPEI/O Instruction Restart DwordThe fields are as follows:••••••••PORT—Intercepted I/O portSZ32—32-bit I/O port sizeSZ16—16-bit I/O port sizeSZ8—8-bit I/O port sizeREP—Repeated port accessSTR—String based port access (INS, OUTS)VAL—Valid (SMI was detected during an I/O instruction.)TYPE—Access type (0 = OUT instruction, 1 = IN instruction).10.4Leaving SMMSoftware leaves SMM and returns to the interrupted program by executing the RSM instruction. RSMcauses the processor to load the interrupted state from the SMRAM state-save area and then transfercontrol back to the interrupted program.
RSM cannot be executed in any mode other than SMM,otherwise an invalid-opcode exception (#UD) occurs.An RSM causes a processor shutdown if an invalid-state condition is found in the SMRAM state-savearea. Only an external reset, external processor-initialization, or non-maskable external interrupt(NMI) can cause the processor to leave the shutdown state.
The invalid SMRAM state-save-areaconditions that can cause a processor shutdown during an RSM are:•••CR0.PE=0 and CR0.PG=1.CR0.CD=0 and CR0.NW=1.Certain reserved bits are set to 1, including:- Any CR0 bit in the range 63–32 is set to 1.- Any unsupported bit in CR3 is set to 1.-284Any unsupported bit in CR4 is set to 1.Any DR6 bit or DR7 bit in the range 63–32 is set to 1.Any unsupported bit in EFER is set to 1.System-Management Mode24593—Rev.
3.13—July 2007••AMD64 TechnologyInvalid returns to long mode, including:- EFER.LME=1, CR0.PG=1, and CR4.PAE=0.- EFER.LME=1, CR0.PG=1, CR4.PAE=1, CS.L=1, and CS.D=1.The SSM revision identifier is modified.Some SMRAM state-save-area conditions are ignored, and the registers, or bits within the registers,are restored in a default manner by the processor. This avoids a processor shutdown when an invalidcondition is stored in SMRAM.
The default conditions restored by the processor are:••••The EFER.LMA register bit is set to the value obtained by logically ANDing the SMRAM valuesof EFER.LME, CR0.PG, and CR4.PAE.The rFLAGS.VM register bit is set to the value obtained by logically ANDing the SMRAM valuesof rFLAGS.VM, CR0.PE, and the inverse of EFER.LMA.The base values of FS, GS, GDTR, IDTR, LDTR, and TR are restored in canonical form.
Thosevalues are sign-extended to bit 63 using the most-significant implemented bit.Unimplemented segment-base bits in the CS, DS, ES, and SS registers are cleared to 0.System-Management Mode285AMD64 Technology28624593—Rev. 3.13—July 2007System-Management Mode24593—Rev. 3.13—July 200711AMD64 Technology128-Bit, 64-Bit, and x87 ProgrammingThis chapter describes the system-software implications of supporting applications that use the 128-bitmedia, 64-bit media, and x87 instructions.
Throughout this chapter, these instructions are collectivelyreferred to as media and x87 (media/x87) instructions. A complete listing of the instructions that fall inthis category—and the detailed operation of each instruction—can be found in volumes 4 and 5. Referto Volume 1 for information on using these instructions in application software.11.1Overview of System-Software ConsiderationsProcessor implementations can support different combinations of the 128-bit media, 64-bit media, andx87 instruction sets.
Two sets of registers—independent of the general-purpose registers—supportthese instructions. The 128-bit media instructions operate on the XMM registers, and the 64-bit mediaand x87-instructions operate on the aliased MMX™/x87 registers. The 128-bit media and x87floating-point instruction sets have special status registers, control registers, exception vectors, andsystem-software control bits for managing the operating environment.
System software that supportsuse of these instructions must be able to manage these resources properly including:•••Detecting support for the instruction set, and enabling any optional features, as necessary.Saving and restoring the processor media or x87 state.Execution of floating-point instructions (media or x87) can produce exceptions. System softwaremust supply exception handlers for all unmasked floating-point exceptions.11.2Determining Media and x87 Feature SupportThe support of 128-bit media, 64-bit media, and x87 instructions is implementation dependent.
Systemsoftware executes the CPUID instruction to determine whether a processor implements any of thesefeatures (see “Processor Feature Identification” on page 61 for more information on using the CPUIDinstruction). After CPUID is executed with function 1 and function 8000_0001h, feature support canbe determined by examining the contents of the ECX and EDX registers.
General guidelines fordetermining feature support are given in the list below. A few instructions belong to more than oneinstruction subset. Refer to “Instruction Subsets and CPUID Feature Sets” in Volume 3 for specificinformation.••128-bit media instructions are supported when:- EDX[25] = 1 for SSE instructions.
(Returned by CPUID function 1.)- EDX[26] = 1 for SSE2 instructions. (Returned by CPUID function 1.)- ECX[0] = 1 for SSE3 instructions. (Returned by CPUID function 1).- ECX[6] = 1 for SSE4A support (Returned by CPUID function 8000_0001h)64-bit media instructions are supported when:- EDX[23]=1 for MMX instructions. (Returned by CPUID 1 and function 8000_0001h.)128-Bit, 64-Bit, and x87 Programming287AMD64 Technology-24593—Rev. 3.13—July 2007EDX[22]=1 for AMD extensions to MMX instructions. (Returned by CPUID function8000_0001h.)EDX[31]=1 for AMD 3DNow!™ instructions. (Returned by CPUID function 8000_0001h.)••EDX[30]=1 for AMD extensions to 3DNow! instructions. (Returned by CPUID function8000_0001h.)x87 floating-point instructions are supported when:- EDX[0]=1.
(Returned by CPUID function 1 and function 8000_0001h.)FXSAVE and FXRSTOR instructions are supported when:- EDX[24]=1. These instructions save and restore the entire media and x87 processor state.(Returned by CPUID function 1 and function 8000_0001h.)If software attempts to execute an instruction belonging to an unsupported instruction subset, aninvalid-opcode exception (#UD) occurs. For a summary of instruction subsets, see “InstructionSubsets and CPUID Feature Sets” in Volume 3.11.3Enabling 128-Bit Media InstructionsUse of the 128-bit media instructions requires system software to support SSE, SSE2, SSE3 and/orSSE4a features, but also the FXSAVE and FXRSTOR instructions, which are used to save and restorethe 128-bit media state (see “FXSAVE and FXRSTOR Instructions” on page 298).
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