Volume 3B System Programming Guide_ Part 2 (794104), страница 23
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Bit 36 specifies other symmetric agenttransactions. Bit 37 specifies central agent transactions. 3FH encoding matchestransactions from any logical processor.•Type_Match (bits 43:38): Specifies transaction types. If all six bits are set, eventcount will include any transaction types.•Snoop_Match: (bits 46:44): The three bits specify (in ascending bit position)clean snoop result, HIT snoop result, and HITM snoop results respectively.••L2_State (bits 53:47): Each bit specifies an L2 coherency state.Core_Select (bits 56:54): Bit 56 enables Core_Select matching.
If bit 56 is clear,Core_select encoding is ignored. If bit 56 is set, the valid encodings for the lowertwo bits (bit 55, 54) are— 00B: Match transactions from only one core (irrespective which core) in thephysical package— 01B: Match transactions from this core and not the other core— 10B: Match transactions from the other core in the physical package, but notthis core— 11B: Match transaction from both cores in the physical package•Block_Snoop (bit 57): specifies blocked snoop.For each counting clock domain, if all six attributes match, event logic signals toincrement the event count field.Vol. 3 18-109DEBUGGING AND PERFORMANCE MONITORINGMSR_EMON_L3_CTR_CTL2/3, Addresses: 107CEH/107CFH6360 59 58 57 56 55 54 5347 4644 43Reserved39 38 37 3632SaturateBlock_snoopCore_selectL2_stateSnoop_matchType_matchAgent_match31032 bit event countFigure 18-40.
MSR_EMON_L3_CTR_CTL2/3, Addresses: 107CEH/107CFH18.20.3 FSB Event InterfaceThe layout of MSR_EMON_L3_CTR_CTL4 through MSR_EMON_L3_CTR_CTL7 is givenin Figure 18-41. Counting starts after software writes a non-zero value to one ormore of the upper 32 bits.The event mask field (bits 58:32) is organized as follows:••Bit 58: must set to 1.FSB_Submask (bits 57:32): Specifies FSB-specific sub-event mask.The FSB sub-event mask defines a set of independent attributes. The event logicsignals to increment the associated event count field if one of the attribute matches.Some of the sub-event mask bit counts durations.
A duration event increments atmost once per cycle.18-110 Vol. 3DEBUGGING AND PERFORMANCE MONITORINGMSR_EMON_L3_CTR_CTL4/5/6/7, Addresses: 107D0H-107D3H6360 59 58 57 56 5550 49 48Reserved39 38 37 36 35 34 33 321SaturateFSB submask31032 bit event countFigure 18-41. MSR_EMON_L3_CTR_CTL4/5/6/7, Addresses: 107D0H-107D3H18.20.3.1 FSB Sub-Event Mask Interface•FSB_type (bit 37:32): Specifies different FSB transaction types originated fromthis physical package•FSB_L_clear (bit 38): Count clean snoop results from any source for transactionoriginated from this physical package•FSB_L_hit (bit 39): Count HIT snoop results from any source for transactionoriginated from this physical package•FSB_L_hitm (bit 40): Count HITM snoop results from any source for transactionoriginated from this physical package••••FSB_L_defer (bit 41): Count DEFER responses to this processor’s transactions•••••FSB_DRDY (bit 45): Count DRDY assertions by this processorFSB_L_retry (bit 42): Count RETRY responses to this processor’s transactionsFSB_L_snoop_stall (bit 43): Count snoop stalls to this processor’s transactionsFSB_DBSY (bit 44): Count DBSY assertions by this processor (without aconcurrent DRDY)FSB_BNR (bit 46): Count BNR assertions by this processorFSB_IOQ_empty (bit 47): Counts each bus clocks when the IOQ is emptyFSB_IOQ_full (bit 48): Counts each bus clocks when the IOQ is fullFSB_IOQ_active (bit 49): Counts each bus clocks when there is at least one entryin the IOQVol.
3 18-111DEBUGGING AND PERFORMANCE MONITORING••FSB_WW_data (bit 50): Counts back-to-back write transaction’s data phase.•FSB_WR_issue (bit 52): Counts back-to-back write-read transaction requestpairs issued by this processor.•FSB_RW_issue (bit 53): Counts back-to-back read-write transaction requestpairs issued by this processor.•FSB_other_DBSY (bit 54): Count DBSY assertions by another agent (without aconcurrent DRDY)••FSB_other_DRDY (bit 55): Count DRDY assertions by another agent•FSB_other_BNR (bit 57): Count BNR assertions from another agentFSB_WW_issue (bit 51): Counts back-to-back write transaction request pairsissued by this processor.FSB_other_snoop_stall (bit 56): Count snoop stalls on the FSB due to anotheragent18.20.4 Common Event Control InterfaceThe MSR_EMON_L3_GL_CTL MSR provides simplified access to query overflow statusof the GBSQ, GSNPQ, FSB event counters.
It also provides control bit fields to freeze,unfreeze, or reset those counters. The following bit fields are supported:•GL_freeze_cmd (bit 0): Freeze the event counters specified by theGL_event_select field.•GL_unfreeze_cmd (bit 1): Unfreeze the event counters specified by theGL_event_select field.•GL_reset_cmd (bit 2): Clear the event count field of the event counters specifiedby the GL_event_select field. The event select field is not affected.•GL_event_select (bit 23:16): Selects one or more event counters to subject tospecified command operations indicated by bits 2:0.
Bit 16 corresponds toMSR_EMON_L3_CTR_CTL0, bit 23 corresponds to MSR_EMON_L3_CTR_CTL7.•GL_event_status (bit 55:48): Indicates the overflow status of each eventcounters. Bit 48 corresponds to MSR_EMON_L3_CTR_CTL0, bit 55 correspondsto MSR_EMON_L3_CTR_CTL7.In the event control field (bits 63:32) of each MSR, if the saturate control (bit 59, seeFigure 18-39 for example) is set, the event logic forces the value FFFF_FFFFH intothe event count field instead of incrementing it.18.21PERFORMANCE MONITORING (P6 FAMILYPROCESSOR)The P6 family processors provide two 40-bit performance counters, allowing twotypes of events to be monitored simultaneously.
These can either count events or18-112 Vol. 3DEBUGGING AND PERFORMANCE MONITORINGmeasure duration. When counting events, a counter increments each time a specified event takes place or a specified number of events takes place. When measuringduration, it counts the number of processor clocks that occur while a specified condition is true. The counters can count events or measure durations that occur at anyprivilege level.Table A-14, Appendix A, lists the events that can be counted with the P6 familyperformance monitoring counters.NOTEThe performance-monitoring events listed in Appendix A areintended to be used as guides for performance tuning. Countervalues reported are not guaranteed to be accurate and should beused as a relative guide for tuning.
Known discrepancies aredocumented where applicable.The performance-monitoring counters are supported by four MSRs: the performanceevent select MSRs (PerfEvtSel0 and PerfEvtSel1) and the performance counter MSRs(PerfCtr0 and PerfCtr1). These registers can be read from and written to using theRDMSR and WRMSR instructions, respectively. They can be accessed using theseinstructions only when operating at privilege level 0. The PerfCtr0 and PerfCtr1 MSRscan be read from any privilege level using the RDPMC (read performance-monitoringcounters) instruction.NOTEThe PerfEvtSel0, PerfEvtSel1, PerfCtr0, and PerfCtr1 MSRs and theevents listed in Table A-14 are model-specific for P6 familyprocessors. They are not guaranteed to be available in other IA-32processors.18.21.1 PerfEvtSel0 and PerfEvtSel1 MSRsThe PerfEvtSel0 and PerfEvtSel1 MSRs control the operation of the performancemonitoring counters, with one register used to set up each counter.
They specify theevents to be counted, how they should be counted, and the privilege levels at whichcounting should take place. Figure 18-42 shows the flags and fields in these MSRs.The functions of the flags and fields in the PerfEvtSel0 and PerfEvtSel1 MSRs are asfollows:•Event select field (bits 0 through 7) — Selects the event logic unit to detectcertain microarchitectural conditions (see Table A-14, for a list of events and their8-bit codes).•Unit mask (UMASK) field (bits 8 through 15) — Further qualifies the eventlogic unit selected in the event select field to detect a specific microarchitecturalcondition.
For example, for some cache events, the mask is used as a MESIprotocol qualifier of cache states (see Table A-14).Vol. 3 18-113DEBUGGING AND PERFORMANCE MONITORING3124 23 22 21 20 19 18 17 16 15Counter Mask(CMASK)IN EV N08 7IUN P E O S Unit Mask (UMASK)S RT CEvent SelectINV—Invert counter maskEN—Enable counters*INT—APIC interrupt enablePC—Pin controlE—Edge detectOS—Operating system modeUSR—User Mode* Only available in PerfEvtSel0.ReservedFigure 18-42.
PerfEvtSel0 and PerfEvtSel1 MSRs•USR (user mode) flag (bit 16) — Specifies that events are counted only whenthe processor is operating at privilege levels 1, 2 or 3. This flag can be used inconjunction with the OS flag.•OS (operating system mode) flag (bit 17) — Specifies that events arecounted only when the processor is operating at privilege level 0. This flag can beused in conjunction with the USR flag.•E (edge detect) flag (bit 18) — Enables (when set) edge detection of events.The processor counts the number of deasserted to asserted transitions of anycondition that can be expressed by the other fields. The mechanism is limited inthat it does not permit back-to-back assertions to be distinguished.
Thismechanism allows software to measure not only the fraction of time spent in aparticular state, but also the average length of time spent in such a state (forexample, the time spent waiting for an interrupt to be serviced).•PC (pin control) flag (bit 19) — When set, the processor toggles the PMi pinsand increments the counter when performance-monitoring events occur; whenclear, the processor toggles the PMi pins when the counter overflows. Thetoggling of a pin is defined as assertion of the pin for a single bus clock followedby deassertion.•INT (APIC interrupt enable) flag (bit 20) — When set, the processorgenerates an exception through its local APIC on counter overflow.•EN (Enable Counters) Flag (bit 22) — This flag is only present in thePerfEvtSel0 MSR.
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