Volume 3B System Programming Guide_ Part 2 (794104), страница 25
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After the counter has been enabled and the prescribed number of events has transpired, the counter will overflow.Approximately 5 clocks later, the overflow is indicated externally and appropriateaction, such as signaling an interrupt, may then be taken.The PM0/BP0 and PM1/BP1 pins also serve to indicate breakpoint matches during incircuit emulation, during which time the counter increment or overflow function ofthese pins is not available.
After RESET, the PM0/BP0 and PM1/BP1 pins are configured for performance monitoring, however a hardware debugger may reconfigurethese pins to indicate breakpoint matches.18.22.3 Events CountedEvents that performance-monitoring counters can be set to count and record (usingCTR0 and CTR1) are divided in two categories: occurrence and duration:•Occurrence events — Counts are incremented each time an event takes place.If PM0/BP0 or PM1/BP1 pins are used to indicate when a counter increments, thepins are asserted each clock counters increment. But if an event happens twice inone clock, the counter increments by 2 (the pins are asserted only once).•Duration events — Counters increment the total number of clocks that thecondition is true.
When used to indicate when counters increment, PM0/BP0and/or PM1/BP1 pins are asserted for the duration.Vol. 3 18-119DEBUGGING AND PERFORMANCE MONITORING18-120 Vol. 3CHAPTER 19INTRODUCTION TO VIRTUAL-MACHINE EXTENSIONS19.1OVERVIEWThis chapter describes the basics of virtual machine architecture and an overview ofthe virtual-machine extensions (VMX) that support virtualization of processor hardware for multiple software environments.Information about VMX instructions is provided in Intel® 64 and IA-32 ArchitecturesSoftware Developer’s Manual, Volume 2B.
Other aspects of VMX and systemprogramming considerations are described in chapters of Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.19.2VIRTUAL MACHINE ARCHITECTUREVirtual-machine extensions define processor-level support for virtual machines onIA-32 processors. Two principal classes of software are supported:•Virtual-machine monitors (VMM) — A VMM acts as a host and has full controlof the processor(s) and other platform hardware. A VMM presents guest software(see next paragraph) with an abstraction of a virtual processor and allows it toexecute directly on a logical processor. A VMM is able to retain selective control ofprocessor resources, physical memory, interrupt management, and I/O.•Guest software — Each virtual machine (VM) is a guest software environmentthat supports a stack consisting of operating system (OS) and applicationsoftware. Each operates independently of other virtual machines and uses on thesame interface to processor(s), memory, storage, graphics, and I/O provided bya physical platform.
The software stack acts as if it were running on a platformwith no VMM. Software executing in a virtual machine must operate with reducedprivilege so that the VMM can retain control of platform resources.19.3INTRODUCTION TO VMX OPERATIONProcessor support for virtualization is provided by a form of processor operationcalled VMX operation.
There are two kinds of VMX operation: VMX root operation andVMX non-root operation. In general, a VMM will run in VMX root operation and guestsoftware will run in VMX non-root operation. Transitions between VMX root operationand VMX non-root operation are called VMX transitions. There are two kinds of VMXtransitions. Transitions into VMX non-root operation are called VM entries.
Transitions from VMX non-root operation to VMX root operation are called VM exits.Vol. 3 19-1INTRODUCTION TO VIRTUAL-MACHINE EXTENSIONSProcessor behavior in VMX root operation is very much as it is outside VMX operation.The principal differences are that a set of new instructions (the VMX instructions) isavailable and that the values that can be loaded into certain control registers arelimited (see Section 19.8).Processor behavior in VMX non-root operation is restricted and modified to facilitatevirtualization. Instead of their ordinary operation, certain instructions (including thenew VMCALL instruction) and events cause VM exits to the VMM. Because theseVM exits replace ordinary behavior, the functionality of software in VMX non-rootoperation is limited.
It is this limitation that allows the VMM to retain control ofprocessor resources.There is no software-visible bit whose setting indicates whether a logical processor isin VMX non-root operation. This fact may allow a VMM to prevent guest software fromdetermining that it is running in a virtual machine.Because VMX operation places restrictions even on software running with currentprivilege level (CPL) 0, guest software can run at the privilege level for which it wasoriginally designed. This capability may simplify the development of a VMM.19.4LIFE CYCLE OF VMM SOFTWAREFigure 19-1 illustrates the life cycle of a VMM and its guest software as well as theinteractions between them. The following items summarize that life cycle:••Software enters VMX operation by executing a VMXON instruction.•VM exits transfer control to an entry point specified by the VMM. The VMM cantake action appropriate to the cause of the VM exit and can then return to thevirtual machine using a VM entry.•Eventually, the VMM may decide to shut itself down and leave VMX operation.
Itdoes so by executing the VMXOFF instruction.Using VM entries, a VMM can then enter guests into virtual machines (one at atime). The VMM effects a VM entry using instructions VMLAUNCH andVMRESUME; it regains control using VM exits.19-2 Vol. 3INTRODUCTION TO VIRTUAL-MACHINE EXTENSIONSGuest 0VM ExitVMXONGuest 1VM EntryVM MonitorVM ExitVMXOFFFigure 19-1. Interaction of a Virtual-Machine Monitor and Guests19.5VIRTUAL-MACHINE CONTROL STRUCTUREVMX non-root operation and VMX transitions are controlled by a data structure calleda virtual-machine control structure (VMCS).Access to the VMCS is managed through a component of processor state called theVMCS pointer (one per logical processor).
The value of the VMCS pointer is the 64-bitaddress of the VMCS. The VMCS pointer is read and written using the instructionsVMPTRST and VMPTRLD. The VMM configures a VMCS using the VMREAD, VMWRITE,and VMCLEAR instructions.A VMM could use a different VMCS for each virtual machine that it supports. For avirtual machine with multiple logical processors (virtual processors), the VMM coulduse a different VMCS for each virtual processor.19.6DISCOVERING SUPPORT FOR VMXBefore system software enters into VMX operation, it must discover the presence ofVMX support in the processor.
System software can determine whether a processorsupports VMX operation using CPUID. If CPUID.1:ECX.VMX[bit 5] = 1, then VMXoperation is supported. See Figure 19-2.Vol. 3 19-3INTRODUCTION TO VIRTUAL-MACHINE EXTENSIONS31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76 5 4 3 21 0ECXCNXT-ID—L1 Context IDTM2—Thermal Monitor 2EST—Enhanced Intel SpeedStep® TechnologyVMX—Virtual Machine ExtensionsDS-CPL—CPL Qual.
Debug StoreMONITOR—Monitor/MwaitSSE3—Streaming SIMD Extensions 3ReservedFigure 19-2. CPUID Extended Feature Information ECXThe VMX architecture is designed to be extensible so that future processors in VMXoperation can support additional features not present in first-generation implementations of the VMX architecture. The availability of extensible VMX features isreported to software using a set of VMX capability MSRs (see Appendix G, “VMXCapability Reporting Facility”).19.7ENABLING AND ENTERING VMX OPERATIONBefore system software can enter VMX operation, it enables VMX by settingCR4.VMXE[bit 13] = 1.
VMX operation is then entered by executing the VMXONinstruction. VMXON causes an invalid-opcode exception (#UD) if executed withCR4.VMXE = 0. Once in VMX operation, it is not possible to clear CR4.VMXE (seeSection 19.8). System software leaves VMX operation by executing the VMXOFFinstruction. CR4.VMXE can be cleared outside of VMX operation after executing ofVMXOFF.VMXON is also controlled by the IA32_FEATURE_CONTROL MSR (MSR address 3AH).This MSR is cleared to zero when a logical processor is reset. The relevant bits of theMSR are:•Bit 0 is the lock bit.
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