Volume 3B System Programming Guide_ Part 2 (794104), страница 28
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3 20-7VIRTUAL-MACHINE CONTROL STRUCTURESTable 20-4. Format of Pending-Debug-ExceptionsBitPosition(s)Bit NameNotes3:0B3 – B0When set, each of these bits indicates that the correspondingbreakpoint condition was met. Any of these bits may be seteven if the corresponding enabling bit in DR7 is not set.11:4ReservedVM entry fails if these bits are not 0. See Section 22.3.1.5.12EnabledbreakpointWhen set, this bit indicates that at least one data or I/Obreakpoint was met and was enabled in DR7.13ReservedVM entry fails if this bit is not 0. See Section 22.3.1.5.14BSWhen set, this bit indicates that a debug exception wouldhave been triggered by single-step execution mode.63:15ReservedVM entry fails if these bits are not 0.
See Section 22.3.1.5.Bits 63:32 exist only on processors that support Intel 64architecture.•VMCS link pointer (64 bits). This field is included for future expansion. Softwareshould set this field to FFFFFFFF_FFFFFFFFH to avoid VM-entry failures (seeSection 22.3.1.5).20.5HOST-STATE AREAThis section describes fields contained in the host-state area of the VMCS.
As notedearlier, processor state is loaded from these fields on every VM exit (see Section23.5).All fields in the host-state area correspond to processor registers:•CR0, CR3, and CR4 (64 bits each; 32 bits on processors that do not support Intel64 architecture).•RSP and RIP (64 bits each; 32 bits on processors that do not support Intel 64architecture).1. For example, execution of a MOV to SS or a POP to SS may inhibit some debug exceptions for oneinstruction. See Section 5.8.3 of Intel® 64 and IA-32 Architectures Software Developer’s Manual,Volume 3A.
In addition, certain events incident to an instruction (for example, an INIT signal) maytake priority over debug traps generated by that instruction. See Table 5-2 in the Intel® 64 andIA-32 Architectures Software Developer’s Manual, Volume 3A.20-8 Vol. 3VIRTUAL-MACHINE CONTROL STRUCTURES•Selector fields (16 bits each) for the segment registers CS, SS, DS, ES, FS, GS,and TR. There is no field in the host-state area for the LDTR selector.•Base-address fields for FS, GS, TR, GDTR, and IDTR (64 bits each; 32 bits onprocessors that do not support Intel 64 architecture).•The following MSRs:— IA32_SYSENTER_CS (32 bits)— IA32_SYSENTER_ESP and IA32_SYSENTER_EIP (64 bits; 32 bits onprocessors that do not support Intel 64 architecture).In addition to the state identified here, some processor state components are loadedwith fixed values on every VM exit; there are no fields corresponding to these components in the host-state area. See Section 23.5 for details of how state is loaded onVM exits.20.6VM-EXECUTION CONTROL FIELDSThe VM-execution control fields govern VMX non-root operation.
These are describedin Section 20.6.1 through Section 20.6.8.20.6.1Pin-Based VM-Execution ControlsThe pin-based VM-execution controls constitute a 32-bit vector that governs thehandling of asynchronous events (for example: interrupts).1 Table 20-5 lists thecontrols supported. See Chapter 21 for how these controls affect processor behaviorin VMX non-root operation.1. Some asynchronous events cause VM exits regardless of the settings of the pin-based VM-execution controls (see Section 21.3).Vol. 3 20-9VIRTUAL-MACHINE CONTROL STRUCTURESTable 20-5. Definitions of Pin-Based VM-Execution ControlsBit Position(s) NameDescription0External-interruptexitingIf this control is 1, external interrupts cause VM exits.Otherwise, they are delivered normally through the guestinterrupt-descriptor table (IDT).
If this control is 1, the valueof RFLAGS.IF does not affect interrupt blocking.3NMI exitingIf this control is 1, non-maskable interrupts (NMIs) causeVM exits. Otherwise, they are delivered normally usingdescriptor 2 of the IDT. This control also determinesinteractions between IRET and blocking by NMI (see Section21.4).5Virtual NMIsIf this control is 1, NMIs are never blocked and the “blockingby NMI” bit (bit 3) in the interruptibility-state field indicates“virtual-NMI blocking” (see Table 20-3).
This control alsointeracts with the “NMI-window exiting” VM-executioncontrol (see Section 20.6.2).This control can be set only if the “NMI exiting” VM-executioncontrol (above) is 1.All other bits in this field are reserved, some to 0 and some to 1. Software shouldconsult the VMX capability MSR IA32_VMX_PINBASED_CTLS (see Appendix G.2) todetermine how to set reserved bits. Failure to set reserved bits properly causessubsequent VM entries to fail (see Section 22.2).20.6.2Processor-Based VM-Execution ControlsThe processor-based VM-execution controls constitute two 32-bit vectors thatgovern the handling of synchronous events, mainly those caused by the execution ofspecific instructions.1 These are the primary processor-based VM-executioncontrols and the secondary processor-based VM-execution controls.Table 20-6 and Table 20-7 list the processor-based VM-execution controls.
SeeChapter 21 for more details of how these controls affect processor behavior in VMXnon-root operation.Bit 31 of the primary processor-based VM-execution controls determines whetherthe secondary processor-based VM-execution controls are used. If that bit is 0, thelogical processor operates as if all the secondary processor-based VM-executioncontrols were 0.
Processors that support only the 0-setting of bit 31 of the primaryprocessor-based VM-execution controls do not support the secondary processorbased VM-execution controls.1. Some instructions cause VM exits regardless of the settings of the processor-based VM-execution controls (see Section 21.1.2), as do task switches (see Section 21.3).20-10 Vol. 3VIRTUAL-MACHINE CONTROL STRUCTURESTable 20-6.
Definitions of Primary Processor-Based VM-Execution ControlsBit Position(s) NameDescription2Interrupt-windowexitingIf this control is 1, a VM exit occurs at the beginning of anyinstruction if RFLAGS.IF = 1 and there are no other blockingof interrupts (see Section 20.4.2).3Use TSC offsettingThis control determines whether executions of RDTSC andexecutions of RDMSR that read from theIA32_TIME_STAMP_COUNTER MSR return a value modifiedby the TSC offset field (see Section 20.6.5 and Section 21.4).7HLT exitingThis control determines whether executions of HLT causeVM exits.9INVLPG exitingThis determines whether executions of INVLPG causeVM exits.10MWAIT exitingThis control determines whether executions of MWAIT causeVM exits.11RDPMC exitingThis control determines whether executions of RDPMC causeVM exits.12RDTSC exitingThis control determines whether executions of RDTSC causeVM exits.19CR8-load exitingThis control determines whether executions of MOV to CR8cause VM exits.
This control must be 0 on processors that donot support Intel 64 architecture.20CR8-store exitingThis control determines whether executions of MOV fromCR8 cause VM exits. This control must be 0 on processorsthat do not support Intel 64 architecture.21Use TPR shadowSetting this control to 1 activates the TPR shadow, which ismaintained in a page of memory addressed by the virtualAPIC address. See Section 21.4.This control must be 0 on processors that do not supportIntel 64 architecture.22NMI-windowexitingIf this control is 1, a VM exit occurs at the beginning of anyinstruction if there is no virtual-NMI blocking (see Section20.4.2).This control can be set only if the “virtual NMIs” VM-executioncontrol (see Section 20.6.1) is 1.23MOV-DR exitingThis control determines whether executions of MOV DRcause VM exits.24Unconditional I/OexitingThis control determines whether executions of I/Oinstructions (IN, INS/INSB/INSW/INSD, OUT, andOUTS/OUTSB/OUTSW/OUTSD) cause VM exits.This control is ignored if the “use I/O bitmaps” control is 1.Vol.
3 20-11VIRTUAL-MACHINE CONTROL STRUCTURESTable 20-6. Definitions of Primary Processor-Based VM-Execution Controls (Contd.)Bit Position(s) NameDescription25This control determines whether I/O bitmaps are used torestrict executions of I/O instructions (see Section 20.6.4 andSection 21.1.3).Use I/O bitmapsFor this control, “0” means “do not use I/O bitmaps” and “1”means “use I/O bitmaps.” If the I/O bitmaps are used, thesetting of the “unconditional I/O exiting” control is ignored.28Use MSR bitmapsThis control determines whether MSR bitmaps are used tocontrol execution of the RDMSR and WRMSR instructions (seeSection 20.6.4 and Section 21.1.3).For this control, “0” means “do not use MSR bitmaps” and “1”means “use MSR bitmaps.” If the MSR bitmaps are not used,all executions of the RDMSR and WRMSR instructions causeVM exits.Not all processors support the 1-setting of this control.Software may consult the VMX capability MSRIA32_VMX_PROCBASED_CTLS (see Appendix G.2) todetermine whether that setting is supported.29MONITOR exitingThis control determines whether executions of MONITORcause VM exits.30PAUSE exitingThis control determines whether executions of PAUSE causeVM exits.31Activate secondary This control determines whether the secondary processorcontrolsbased VM-execution controls are used.
If this control is 0, thelogical processor operates as if all the secondary processorbased VM-execution controls were also 0.Table 20-7. Definitions of Secondary Processor-Based VM-Execution ControlsBit Position(s) NameDescription0If this control is 1, a VM exit occurs on any attempt to accessdata on the page with the APIC-access address. See Section21.2.Virtualize APICaccessesAll other bits in these fields are reserved, some to 0 and some to 1. Software shouldconsult the VMX capability MSRs IA32_VMX_PROCBASED_CTLS andIA32_VMX_PROCBASED_CTLS2 (see Appendix G.2) to determine how to setreserved bits. Failure to set reserved bits properly causes subsequent VM entries tofail (see Section 22.2).20-12 Vol.
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