Volume 3B System Programming Guide_ Part 2 (794104), страница 30
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The vector is stored in the VM-exitinterruption-information field, which is marked valid.• If such a VM exit occurs and this control is 0, the interruptis not acknowledged and the VM-exit interruptioninformation field is marked invalid.NOTES:1. Since Intel 64 architecture specifies that IA32_EFER.LMA is always set to the logical-AND ofCR0.PG and IA32_EFER.LME, and since CR0.PG is always 1 in VMX operation, IA32_EFER.LMA isalways identical to IA32_EFER.LME in VMX operation.20-16 Vol.
3VIRTUAL-MACHINE CONTROL STRUCTURESAll other bits in this field are reserved, some to 0 and some to 1. Software shouldconsult the VMX capability MSR IA32_VMX_EXIT_CTLS (see Appendix G.3) to determine how it should set the reserved bits. Failure to set reserved bits properly causessubsequent VM entries to fail (see Section 22.2).20.7.2VM-Exit Controls for MSRsA VMM may specify lists of MSRs to be stored and loaded on VM exits. The followingVM-exit control fields determine how MSRs are stored on VM exits:•VM-exit MSR-store count (32 bits).
This field specifies the number of MSRs tobe stored on VM exit. It is recommended that this count not exceed 512 bytes.1Otherwise, unpredictable processor behavior (including a machine check) mayresult during VM exit.•VM-exit MSR-store address (64 bits). This field contains the physical addressof the VM-exit MSR-store area. The area is a table of entries, 16 bytes per entry,where the number of entries is given by the VM-exit MSR-store count. The formatof each entry is given in Table 20-9. If the VM-exit MSR-store count is not zero,the address must be 16-byte aligned.Table 20-9.
Format of an MSR EntryBit Position(s) Contents31:0MSR index63:32Reserved127:64MSR dataSee Section 23.4 for how this area is used on VM exits.The following VM-exit control fields determine how MSRs are loaded on VM exits:•VM-exit MSR-load count (32 bits). This field contains the number of MSRs tobe loaded on VM exit. It is recommended that this count not exceed 512 bytes.Otherwise, unpredictable processor behavior (including a machine check) mayresult during VM exit.21. Future implementations may allow more MSRs to be stored reliably.
Software should consult theVMX capability MSR IA32_VMX_MISC to determine the number supported (see Appendix G.5).2. Future implementations may allow more MSRs to be loaded reliably. Software should consult theVMX capability MSR IA32_VMX_MISC to determine the number supported (see Appendix G.5).Vol. 3 20-17VIRTUAL-MACHINE CONTROL STRUCTURES•VM-exit MSR-load address (64 bits). This field contains the physical address ofthe VM-exit MSR-load area. The area is a table of entries, 16 bytes per entry,where the number of entries is given by the VM-exit MSR-load count (seeTable 20-9).
If the VM-exit MSR-load count is not zero, the address must be16-byte aligned.See Section 23.6 for how this area is used on VM exits.20.8VM-ENTRY CONTROL FIELDSThe VM-entry control fields govern the behavior of VM entries. They are discussed inSections 20.8.1 through 20.8.3.20.8.1VM-Entry ControlsThe VM-entry controls constitute a 32-bit vector that governs the basic operation ofVM entries. Table 20-10 lists the controls supported. See Chapter 22 for how thesecontrols affect VM entries.Table 20-10. Definitions of VM-Entry ControlsBit Position(s) Name9DescriptionIA-32e mode guest On processors that support Intel 64 architecture, this controldetermines whether the logical processor is in IA-32e modeafter VM entry.
Its value is loaded into IA32_EFER.LMA andIA32_EFER.LME as part of VM entry.1This control must be 0 on processors that do not supportIntel 64 architecture.10Entry to SMMThis control determines whether the logical processor is insystem-management mode (SMM) after VM entry. Thiscontrol must be 0 for any VM entry from outside SMM.11Deactivate dualmonitor treatmentIf set to 1, the default treatment of SMIs and SMM is in effectafter the VM entry (see Section 24.16.7). This control mustbe 0 for any VM entry from outside SMM.NOTES:1. Since Intel 64 architecture specifies that IA32_EFER.LMA is always set to the logical-AND ofCR0.PG and IA32_EFER.LME, and since CR0.PG is always 1 in VMX operation; IA32_EFER.LMA isalways identical to IA32_EFER.LME in VMX operation.All other bits in this field are reserved, some to 0 and some to 1.
Software shouldconsult the VMX capability MSR IA32_VMX_ENTRY_CTLS (see Appendix G.4) todetermine how it should set the reserved bits. Failure to set reserved bits properlycauses subsequent VM entries to fail (see Section 22.2).20-18 Vol. 3VIRTUAL-MACHINE CONTROL STRUCTURES20.8.2VM-Entry Controls for MSRsA VMM may specify a list of MSRs to be loaded on VM entries. The following VM-entrycontrol fields manage this functionality:•VM-entry MSR-load count (32 bits).
This field contains the number of MSRs tobe loaded on VM entry. It is recommended that this count not exceed 512 bytes.Otherwise, unpredictable processor behavior (including a machine check) mayresult during VM entry.1•VM-entry MSR-load address (64 bits). This field contains the physical addressof the VM-entry MSR-load area.
The area is a table of entries, 16 bytes per entry,where the number of entries is given by the VM-entry MSR-load count. Theformat of entries is described in Table 20-9. If the VM-entry MSR-load count is notzero, the address must be 16-byte aligned.See Section 22.4 for details of how this area is used on VM entries.20.8.3VM-Entry Controls for Event InjectionVM entry can be configured to conclude by delivering an event through the guest IDT(after all guest state and MSRs have been loaded).
This process is called eventinjection and is controlled by the following three VM-entry control fields:•VM-entry interruption-information field (32 bits). This field provides detailsabout the event to be injected. Table 20-11 describes the field.Table 20-11. Format of the VM-Entry Interruption-Information FieldBitPosition(s)Content7:0Vector of interrupt or exception10:8Interruption type:0: External interrupt1: Reserved2: Non-maskable interrupt (NMI)3: Hardware exception4: Software interrupt5: Privileged software exception6: Software exception7: Reserved11Deliver error code (0 = do not deliver; 1 = deliver)30:12Reserved31Valid1. Future implementations may allow more MSRs to be loaded reliably.
Software should consult theVMX capability MSR IA32_VMX_MISC to determine the number supported (see Appendix G.5).Vol. 3 20-19VIRTUAL-MACHINE CONTROL STRUCTURES— The vector (bits 7:0) determines which entry in the IDT is used.— The interruption type (bits 10:8) determines details of how the injection isperformed. In general, a VMM should use the type hardware exception forall exceptions other than breakpoint exceptions (#BP; generated by INT3)and overflow exceptions (#OF; generated by INTO); it should use the typesoftware exception for #BP and #OF.— For exceptions, the deliver-error-code bit (bit 11) determines whetherdelivery pushes an error code on the guest stack.— VM entry injects an event if and only if the valid bit (bit 31) is 1.•VM-entry exception error code (32 bits).
This field is used if and only if thevalid bit (bit 31) and the deliver-error-code bit (bit 11) are both set in theVM-entry interruption-information field.•VM-entry instruction length (32 bits). For injection of events whose type issoftware interrupt, software exception, or privileged software exception, thisfield is used to determine the value of RIP that is pushed on the stack.See Section 22.5 for details regarding the mechanics of event injection, including theuse of the interruption type and the VM-entry instruction length.VM exits clear the valid bit (bit 31) in the VM-entry interruption-information field.20.9VM-EXIT INFORMATION FIELDSThe VMCS contains a section of read-only fields that contain information about themost recent VM exit. Attempts to write to these fields with VMWRITE fail (see“VMWRITE—Write Field to Virtual-Machine Control Structure” in Chapter 5 of theIntel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B).20.9.1Basic VM-Exit InformationThe following VM-exit information fields provide basic information about a VM exit:•Exit reason (32 bits).
This field encodes the reason for the VM exit and has thestructure given in Table 20-12.20-20 Vol. 3VIRTUAL-MACHINE CONTROL STRUCTURESTable 20-12. Format of Exit ReasonBitPosition(s)Contents15:0Basic exit reason28:16Reserved (cleared to 0)29VM exit from VMX root operation30Reserved (cleared to 0)31VM-entry failure (0 = true VM exit; 1 = VM-entry failure)— Bits 15:0 provide basic information about the cause of the VM exit (if bit 31 isclear) or of the VM-entry failure (if bit 31 is set). Appendix I enumerates thebasic exit reasons.— Bit 29 is set if and only if the processor was in VMX root operation at the timethe VM exit occurred. This can happen only for SMM VM exits.
See Section24.16.2.— Because some VM-entry failures load processor state from the host-statearea (see Section 22.7), software must be able to distinguish such cases fromtrue VM exits. Bit 31 is used for that purpose.•Exit qualification (64 bits; 32 bits on processors that do not support Intel 64architecture). This field contains additional information about the cause ofVM exits due to the following: debug exceptions; page-fault exceptions; start-upIPIs (SIPIs); task switches; INVLPG; VMCLEAR; VMPTRLD; VMPTRST; VMREAD;VMWRITE; VMXON; control-register accesses; MOV DR; I/O instructions; andMWAIT.
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