Volume 3B System Programming Guide_ Part 2 (794104), страница 26
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If this bit is clear, VMXON causes a general-protectionexception. If the lock bit is set, WRMSR to this MSR causes a general-protectionexception. Once the lock bit is set, the MSR cannot be modified until a power-upreset condition. System BIOS can use this bit to provide a setup option for BIOSto disable support for VMX.
To enable VMX support in a platform, BIOS must setbit 2 (see below) as well as the lock bit.19-4 Vol. 3INTRODUCTION TO VIRTUAL-MACHINE EXTENSIONS•Bit 2 enables VMXON. If this bit is clear, VMXON causes a general-protectionexception.Before executing VMXON, software should allocate a naturally aligned 4-KByte regionof memory that a logical processor may use to support VMX operation.1 This regionis called the VMXON region. The address of the VMXON region (the VMXON pointer)is provided in an operand to VMXON.
Section 20.10.4, “VMXON Region,” details howsoftware should initialize and access the VMXON region.19.8RESTRICTIONS ON VMX OPERATIONVMX operation places restrictions on processor operation. These are detailed below:•In VMX operation, processors may fix certain bits in CR0 and CR4 to specificvalues and not support other values. VMXON fails if any of these bits contains anunsupported value (see “VMXON—Enter VMX Operation” in Chapter 5 of theIntel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 2B).Any attempt to set one of these bits to an unsupported value while in VMXoperation (including VMX root operation) using any of the CLTS, LMSW, or MOVCR instructions causes a general-protection exception.
VM entry or VM exitcannot set any of these bits to an unsupported value.2NOTEThe first processors to support VMX operation require that thefollowing bits be 1 in VMX operation: CR0.PE, CR0.NE, CR0.PG, andCR4.VMXE. The restrictions on CR0.PE and CR0.PG imply that VMXoperation is supported only in paged protected mode (includingIA-32e mode). Therefore, guest software cannot be run in unpagedprotected mode or in real-address mode. See Section 25.2,“Supporting Processor Operating Modes in Guest Environments,” fora discussion of how a VMM might support guest software that expectsto run in unpaged protected mode or in real-address mode.•VMXON fails if a logical processor is in A20M mode (see “VMXON—Enter VMXOperation” in Chapter 5 of the Intel® 64 and IA-32 Architectures SoftwareDeveloper’s Manual, Volume 2B).
Once the processor is in VMX operation, A20Minterrupts are blocked. Thus, it is impossible to be in A20M mode in VMXoperation.1. Future processors may require that a different amount of memory be reserved. If so, this fact isreported to software using the VMX capability-reporting mechanism.2. Software should consult the VMX capability MSRs IA32_VMX_CR0_FIXED0 andIA32_VMX_CR0_FIXED1 to determine how bits in CR0 are set.
(see Appendix G.6). For CR4, software should consult the VMX capability MSRs IA32_VMX_CR4_FIXED0 andIA32_VMX_CR4_FIXED1 (see Appendix G.7).Vol. 3 19-5INTRODUCTION TO VIRTUAL-MACHINE EXTENSIONS•The INIT signal is blocked whenever a logical processor is in VMX root operation.It is not blocked in VMX non-root operation. Instead, INITs cause VM exits (seeSection 21.3, “Other Causes of VM Exits”).19-6 Vol.
3CHAPTER 20VIRTUAL-MACHINE CONTROL STRUCTURES20.1OVERVIEWThe virtual-machine control data structure (VMCS) is defined for VMX operation. AVMCS manages transitions in and out of VMX non-root operation (VM entries andVM exits) as well as processor behavior in VMX non-root operation. This structure ismanipulated by the new instructions VMCLEAR, VMPTRLD, VMREAD, and VMWRITE.A VMM can use a different VMCS for each virtual machine that it supports. For avirtual machine with multiple logical processors (virtual processors), the VMM canuse a different VMCS for each virtual processor.Each logical processor associates a region in memory with each VMCS.
This region iscalled the VMCS region.1 Software references a specific VMCS by using the 64-bitphysical address of the region; such an address is called a VMCS pointer. VMCSpointers must be aligned on a 4-KByte boundary (bits 11:0 must be zero). Onprocessors that support Intel 64 architecture, these pointers must not set bitsbeyond the processor’s physical-address width.2 On processors that do not supportIntel 64 architecture, they must not set any bits in the range 63:32.A logical processor may maintain any number of active VMCSs. At any given time,one is the current VMCS:•Software makes a VMCS active by executing VMPTRLD with the address of theVMCS. The processor may optimize VMX operation by maintaining the state of anactive VMCS in memory, on the processor, or both.
Software should not make aVMCS active on more than one logical processor (see Section 20.10.1 for how tomigrate a VMCS from one logical processor to another). Software makes a VMCSinactive by executing VMCLEAR with the address of the VMCS. A logical processordoes not use an inactive VMCS or maintain its state on the processor.If VMXOFF is executed while a VMCS is active, the VMCS data in the corresponding VMCS region are undefined after execution of VMXOFF. Software canavoid this problem by avoiding execution of VMXOFF while a VMCS is active.•Software makes a VMCS current by executing VMPTRLD with the address of theVMCS; that address is loaded into the current-VMCS pointer.
VMX instructionsVMLAUNCH, VMPTRST, VMREAD, VMRESUME, and VMWRITE operate on thecurrent VMCS. In particular, the VMPTRST instruction stores the current-VMCS1. The amount of memory required for a VMCS region is at most 4 KBytes. The exact size is implementation specific and can be determined by consulting the VMX capability MSRIA32_VMX_BASIC to determine the size of the VMCS region (see Appendix G.1).2. Software can determine a processor’s physical-address width by executing CPUID with80000008H in EAX.
The physical-address width is returned in bits 7:0 of EAX.Vol. 3 20-1VIRTUAL-MACHINE CONTROL STRUCTURESpointer into a specified memory location (it stores the value FFFFFFFF_FFFFFFFFHif there is no current VMCS). A VMCS remains current until either softwareexecutes VMPTRLD with the address of a different VMCS (which then becomesthe current VMCS) or software executes VMCLEAR with the address of the currentVMCS (after which there is no current VMCS).This document frequently uses the term “the VMCS” to refer to the current VMCS.20.2FORMAT OF THE VMCS REGIONA VMCS region comprises up to 4-KBytes.1 The format of a VMCS region is given inTable 20-1.Table 20-1.
Format of the VMCS RegionByte OffsetContents0VMCS revision identifier4VMX-abort indicator8VMCS data (implementation-specific format)The first 32 bits of the VMCS region contain the VMCS revision identifier. Processors that maintain VMCS data in different formats (see below) use different VMCSrevision identifiers. These identifiers enable software to avoid using a VMCS regionformatted for one processor on a processor that uses a different format.Software should write the VMCS revision identifier to the VMCS region before usingthat region for a VMCS. The VMCS revision identifier is never written by theprocessor; VMPTRLD may fail if its operand references a VMCS region whose VMCSrevision identifier differs from that used by the processor.
Software can discover theVMCS revision identifier that a processor uses by reading the VMX capability MSRIA32_VMX_BASIC (see Appendix G, “VMX Capability Reporting Facility”).The next 32 bits of the VMCS region are used for the VMX-abort indicator. Thecontents of these bits do not control processor operation in any way. A logicalprocessor writes a non-zero value into these bits if a VMX abort occurs (see Section23.7). Software may also write into this field.The remainder of the VMCS region is used for VMCS data (those parts of the VMCSthat control VMX non-root operation and the VMX transitions).
The format of thesedata is implementation-specific. VMCS data are discussed in Section 20.3 throughSection 20.9. To ensure proper behavior in VMX operation, software should maintainthe VMCS region and related structures (enumerated in Section 20.10.3) in1. The exact size is implementation specific and can be determined by consulting the VMX capability MSR IA32_VMX_BASIC to determine the size of the VMCS region (see Appendix G.1).20-2 Vol. 3VIRTUAL-MACHINE CONTROL STRUCTURESwriteback cacheable memory. Future implementations may allow or require adifferent memory type1. Software should consult the VMX capability MSRIA32_VMX_BASIC (see Appendix G.1).20.3ORGANIZATION OF VMCS DATAThe VMCS data are organized into six logical groups:•Guest-state area.
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