Volume 3B System Programming Guide_ Part 2 (794104), страница 21
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For events that are marked as TI in AppendixA, the effect of selectively specifying T0_USR, T0_OS, T1_USR, T1_OS bits is shownin Table 18-21.Vol. 3 18-95DEBUGGING AND PERFORMANCE MONITORINGTable 18-21. Effect of Logical Processor and CPL Qualificationfor Non-logical-Processor-specific (TI) EventsT1_OS/T1_USR =00T1_OS/T1_USR =01T1_OS/T1_USR =11T1_OS/T1_USR =10T0_OS/T0_USR =00Zero countCounts while (a)T0 in USR or (b)T1 in USRCountsirrespective ofCPL, T0, T1Counts while (a)T0 in OS or (b) T1in OST0_OS/T0_USR =01Counts while (a)T0 in USR or (b)T1 in USRCounts while (a)T0 in USR or (b)T1 in USRCountsirrespective ofCPL, T0, T1Countsirrespective ofCPL, T0, T1T0_OS/T0_USR =11Countsirrespective ofCPL, T0, T1Countsirrespective ofCPL, T0, T1Countsirrespective ofCPL, T0, T1Countsirrespective ofCPL, T0, T1T0_OS/T0_USR =0Counts while (a)T0 in OS or (b) T1in OSCountsirrespective ofCPL, T0, T1Countsirrespective ofCPL, T0, T1Counts while (a)T0 in OS or (b) T1in OS18.17COUNTING CLOCKSThe count of cycles, also known as clockticks, forms a the basis for measuring howlong a program takes to execute.
Clockticks are also used as part of efficiency ratioslike cycles per instruction (CPI). Processor clocks may stop ticking under circumstances like the following:•The processor is halted when there is nothing for the CPU to do. For example, theprocessor may halt to save power while the computer is servicing an I/O request.When Hyper-Threading Technology is enabled, both logical processors must behalted for performance-monitoring counters to be powered down.•The processor is asleep as a result of being halted or because of a powermanagement scheme.
There are different levels of sleep. In the some deep sleeplevels, the time-stamp counter stops counting.In addition, processor core clocks may undergo transitions at different ratios relativeto the processor’s bus clock frequency. Some of the situations that can causeprocessor core clock to undergo frequency transitions include:••TM2 transitionsEnhanced Intel SpeedStep Technology transitions (P-state transitions)For Intel processors that support Intel Dynamic Acceleration or XE operation, theprocessor core clocks may operate at a frequency that differs from the maximumqualified frequency (as indicated by brand string information reported by CPUIDinstruction). See Section 18.17.5 for more detail.18-96 Vol.
3DEBUGGING AND PERFORMANCE MONITORINGThere are several ways to count processor clock cycles to monitor performance.These are:•Non-halted clockticks — Measures clock cycles in which the specified logicalprocessor is not halted and is not in any power-saving state. When HyperThreading Technology is enabled, ticks can be measured on a per-logicalprocessor basis. There are also performance events on dual-core processors thatmeasure clockticks per logical processor when the processor is not halted.•Non-sleep clockticks — Measures clock cycles in which the specified physicalprocessor is not in a sleep mode or in a power-saving state.
These ticks cannot bemeasured on a logical-processor basis.•Time-stamp counter — Measures clock cycles in which the physical processor isnot in deep sleep. These ticks cannot be measured on a logical-processor basis.•Reference clockticks — TM2 or Enhanced Intel SpeedStep technology are twoexamples of processor features that can cause processor core clockticks torepresent non-uniform tick intervals due to change of bus ratios.
Performanceevents that counts clockticks of a constant reference frequency was introducedIntel Core Duo and Intel Core Solo processors. The mechanism is furtherenhanced on processors based on Intel Core microarchitecture.Some processor models permit clock cycles to be measured when the physicalprocessor is not in deep sleep (by using the time-stamp counter and the RDTSCinstruction). Note that such ticks cannot be measured on a per-logical-processorbasis. See Section 18.10, “Time-Stamp Counter,” for detail on processor capabilities.The first two methods use performance counters and can be set up to cause an interrupt upon overflow (for sampling).
They may also be useful where it is easier for atool to read a performance counter than to use a time stamp counter (the timestampcounter is accessed using the RDTSC instruction).For applications with a significant amount of I/O, there are two ratios of interest:•Non-halted CPI — Non-halted clockticks/instructions retired measures the CPIfor phases where the CPU was being used. This ratio can be measured on alogical-processor basis when Hyper-Threading Technology is enabled.•Nominal CPI — Time-stamp counter ticks/instructions retired measures the CPIover the duration of a program, including those periods when the machine haltswhile waiting for I/O.18.17.1Non-Halted ClockticksUse the following procedure to program ESCRs and CCCRs to obtain non-haltedclockticks on processors based on Intel NetBurst microarchitecture:1.
Select an ESCR for the global_power_events and specify the RUNNING sub-eventmask and the desired T0_OS/T0_USR/T1_OS/T1_USR bits for the targetedprocessor.Vol. 3 18-97DEBUGGING AND PERFORMANCE MONITORING2. Select an appropriate counter.3. Enable counting in the CCCR for that counter by setting the enable bit.18.17.2Non-Sleep ClockticksPerformance monitoring counters can be configured to count clockticks whenever theperformance monitoring hardware is not powered-down. To count Non-sleep Clockticks with a performance-monitoring counter, do the following:1. Select one of the 18 counters.2.
Select any of the ESCRs whose events the selected counter can count. Set itsevent select to anything other than no_event. This may not seem necessary, butthe counter may be disabled if this is not done.3. Turn threshold comparison on in the CCCR by setting the compare bit to 1.4.
Set the threshold to 15 and the complement to 1 in the CCCR. Since no event canexceed this threshold, the threshold condition is met every cycle and the countercounts every cycle. Note that this overrides any qualification (e.g. by CPL)specified in the ESCR.5. Enable counting in the CCCR for the counter by setting the enable bit.In most cases, the counts produced by the non-halted and non-sleep metrics areequivalent if the physical package supports one logical processor and is not placed ina power-saving state.
Operating systems may execute an HLT instruction and place aphysical processor in a power-saving state.On processors that support Hyper-Threading Technology (HT), each physical packagecan support two or more logical processors. Current implementation of HT providestwo logical processors for each physical processor. While both logical processors canexecute two threads simultaneously, one logical processor may halt to allow theother logical processor to execute without sharing execution resources between twological processors.Non-halted Clockticks can be set up to count the number of processor clock cycles foreach logical processor whenever the logical processor is not halted (the count mayinclude some portion of the clock cycles for that logical processor to complete a transition to a halted state).
Physical processors that support HT enter into a powersaving state if all logical processors halt.The Non-sleep Clockticks mechanism uses a filtering mechanism in CCCRs. Themechanism will continue to increment as long as one logical processor is not haltedor in a power-saving state. Applications may cause a processor to enter into a powersaving state by using an OS service that transfers control to an OS’s idle loop.
Theidle loop then may place the processor into a power-saving state after an implementation-dependent period if there is no work for the processor.18-98 Vol. 3DEBUGGING AND PERFORMANCE MONITORING18.17.3Incrementing the Time-Stamp CounterThe time-stamp counter increments when the clock signal on the system bus isactive and when the sleep pin is not asserted. The counter value can be read with theRDTSC instruction.The time-stamp counter and the non-sleep clockticks count may not agree in allcases and for all processors.
See Section 18.10, “Time-Stamp Counter,” for moreinformation on counter operation.18.17.4Non-Halted Reference ClockticksSoftware can use either processor-specific performance monitor events (forexample: CPU_CLK_UNHALTED.BUS on processors based on the Intel Core microarchitecture, and equivalent event specifications on the Intel Core Duo and Intel CoreSolo processors) to count non-halted reference clockticks.These events count reference clock cycles whenever the specified processor is nothalted.
The counter counts reference cycles associated with a fixed-frequency clocksource irrespective of P-state, TM2, or frequency transitions that may occur to theprocessor.18.17.5Cycle Counting and Opportunistic Processor OperationAs a result of the state transitions due to opportunistic processor performance operation (see Chapter 13, “Power and Thermal Management”), a logical processor or aprocessor core can operate at frequency different from that indicated by theprocessor’s maximum qualified frequency.The following items are expected to hold true irrespective of when opportunisticprocessor operation causes state transitions:••The time stamp counter operates at a fixed-rate frequency of the processor.•The IA32_FIXED_CTR2 counter increments at the same TSC frequencyirrespective of any transitions caused by opportunistic processor operation.•The Local APIC timer operation is unaffected by opportunistic processoroperation.•The TSC, IA32_MPERF, and IA32_FIXED_CTR2 operate at the same, maximumresolved frequency of the platform, which is equal to the product of scalable busfrequency and maximum resolved bus ratio.The IA32_MPERF counter increments at the same TSC frequency irrespective ofany transitions caused by opportunistic processor operation.For processors based on Intel Core microarchitecture, the scalable bus frequency isencoded in the bit field MSR_FSB_FREQ[2:0] at (0CDH), see Appendix B, “Model-Vol.
3 18-99DEBUGGING AND PERFORMANCE MONITORINGSpecific Registers (MSRs)”. The maximum resolved bus ratio can be read from thefollowing bit field:•If XE operation is disabled, the maximum resolved bus ratio can be read inMSR_PLATFORM_ID[12:8]. It corresponds to the maximum qualified frequency.•IF XE operation is enabled, the maximum resolved bus ratio is given inMSR_PERF_STAT[44:40], it corresponds to the maximum XE operationfrequency configured by BIOS.XE operation of an Intel 64 processor is implementation specific.
XE operation can beenabled only by BIOS. If MSR_PERF_STAT[31] is set, XE operation is enabled. TheMSR_PERF_STAT[31] field is read-only.18.18PERFORMANCE MONITORING AND DUAL-CORETECHNOLOGYThe performance monitoring capability of dual-core processors duplicates themicroarchitectural resources of a single-core processor implementation. Eachprocessor core has dedicated performance monitoring resources.In the case of Pentium D processor, each logical processor is associated with dedicated resources for performance monitoring. In the case of Pentium processorExtreme edition, each processor core has dedicated resources, but two logicalprocessors in the same core share performance monitoring resources (see Section18.16, “Performance Monitoring and Hyper-Threading Technology”).18.19PERFORMANCE MONITORING ON 64-BIT INTEL XEONPROCESSOR MP WITH UP TO 8-MBYTE L3 CACHEThe 64-bit Intel Xeon processor MP with up to 8-MByte L3 cache has a CPUID signature of family [0FH], model [03H or 04H].
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