Volume 3B System Programming Guide_ Part 2 (794104), страница 20
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Theseprivilege levels are generally used by application code and unprotected operatingsystem code.Reserved31 3025 24EventSelect5 4 3 2 1 09 8TagValueEvent MaskTag EnableT0_OST0_USRT1_OST1_USR6332ReservedFigure 18-31. Event Selection Control Register (ESCR) for the Pentium 4 Processor,Intel Xeon Processor and Intel Xeon Processor MP Supporting Hyper-ThreadingTechnology•T1_OS flag, bit 1 — When set, events are counted when thread 1 (logicalprocessor 1) is executing at CPL of 0. This privilege level is generally reserved forprotected operating system code. (When both the T1_OS and T1_USR flags areset, thread 1 events are counted at all privilege levels.)•T0_USR flag, bit 2 — When set, events are counted when thread 0 (logicalprocessor 0) is executing at a CPL of 1, 2, or 3.•T0_OS flag, bit 3 — When set, events are counted when thread 0 (logicalprocessor 0) is executing at CPL of 0. (When both the T0_OS and T0_USR flagsare set, thread 0 events are counted at all privilege levels.)Vol.
3 18-91DEBUGGING AND PERFORMANCE MONITORING•Tag enable, bit 4 — When set, enables tagging of μops to assist in at-retirementevent counting; when clear, disables tagging. See Section 18.15.7, “AtRetirement Counting.”•Tag value field, bits 5 through 8 — Selects a tag value to associate with a μopto assist in at-retirement event counting.•Event mask field, bits 9 through 24 — Selects events to be counted from theevent class selected with the event select field.•Event select field, bits 25 through 30) — Selects a class of events to becounted.
The events within this class that are counted are selected with the eventmask field.The T0_OS and T0_USR flags and the T1_OS and T1_USR flags allow event countingand sampling to be specified for a specific logical processor (0 or 1) within an IntelXeon processor MP (See also: Section 7.5.5, “Identifying Logical Processors in an MPSystem,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual,Volume 3A).Not all performance monitoring events can be detected within an Intel Xeonprocessor MP on a per logical processor basis (see Section 18.16.4, “PerformanceMonitoring Events”).
Some sub-events (specified by an event mask bits) are countedor sampled without regard to which logical processor is associated with the detectedevent.18.16.2 CCCR MSRsFigure 18-32 shows the layout of a CCCR MSR in processors supporting HyperThreading Technology. The functions of the flags and fields are as follows:•Enable flag, bit 12 — When set, enables counting; when clear, the counter isdisabled. This flag is cleared on reset•ESCR select field, bits 13 through 15 — Identifies the ESCR to be used toselect events to be counted with the counter associated with the CCCR.•Active thread field, bits 16 and 17 — Enables counting depending on whichlogical processors are active (executing a thread).
This field enables filtering ofevents based on the state (active or inactive) of the logical processors. Theencodings of this field are as follows:00 — None. Count only when neither logical processor is active.01 — Single. Count only when one logical processor is active (either 0 or 1).10 — Both. Count only when both logical processors are active.11 — Any. Count when either logical processor is active.A halted logical processor or a logical processor in the “wait for SIPI” state isconsidered inactive.18-92 Vol.
3DEBUGGING AND PERFORMANCE MONITORING•Compare flag, bit 18 — When set, enables filtering of the event count; whenclear, disables filtering. The filtering method is selected with the threshold,complement, and edge flags.Reserved31 30 2927 26 25 24 2320 19 18 17 16 15Threshold13 12 11ESCRSelect0ReservedReservedEnableActive ThreadCompareComplementEdgeFORCE_OVFOVF_PMI_T0OVF_PMI_T1CascadeOVF6332ReservedFigure 18-32. Counter Configuration Control Register (CCCR)•Complement flag, bit 19 — Selects how the incoming event count is comparedwith the threshold value. When set, event counts that are less than or equal tothe threshold value result in a single count being delivered to the performancecounter; when clear, counts greater than the threshold value result in a countbeing delivered to the performance counter (see Section 18.15.6.2, “FilteringEvents”). The compare flag is not active unless the compare flag is set.•Threshold field, bits 20 through 23 — Selects the threshold value to be usedfor comparisons.
The processor examines this field only when the compare flag isset, and uses the complement flag setting to determine the type of thresholdcomparison to be made. The useful range of values that can be entered in thisfield depend on the type of event being counted (see Section 18.15.6.2, “FilteringEvents”).•Edge flag, bit 24 — When set, enables rising edge (false-to-true) edgedetection of the threshold comparison output for filtering event counts; whenclear, rising edge detection is disabled. This flag is active only when the compareflag is set.Vol.
3 18-93DEBUGGING AND PERFORMANCE MONITORING•FORCE_OVF flag, bit 25 — When set, forces a counter overflow on everycounter increment; when clear, overflow only occurs when the counter actuallyoverflows.•OVF_PMI_T0 flag, bit 26 — When set, causes a performance monitor interrupt(PMI) to be sent to logical processor 0 when the counter overflows occurs; whenclear, disables PMI generation for logical processor 0. Note that the PMI isgenerate on the next event count after the counter has overflowed.•OVF_PMI_T1 flag, bit 27 — When set, causes a performance monitor interrupt(PMI) to be sent to logical processor 1 when the counter overflows occurs; whenclear, disables PMI generation for logical processor 1.
Note that the PMI isgenerate on the next event count after the counter has overflowed.•Cascade flag, bit 30 — When set, enables counting on one counter of a counterpair when its alternate counter in the other the counter pair in the same countergroup overflows (see Section 18.15.2, “Performance Counters,” for furtherdetails); when clear, disables cascading of counters.•OVF flag, bit 31 — Indicates that the counter has overflowed when set.
This flagis a sticky flag that must be explicitly cleared by software.18.16.3 IA32_PEBS_ENABLE MSRIn a processor supporting Hyper-Threading Technology and based on the IntelNetBurst microarchitecture, PEBS is enabled and qualified with two bits in theMSR_PEBS_ENABLE MSR: bit 25 (ENABLE_PEBS_MY_THR) and 26(ENABLE_PEBS_OTH_THR) respectively. These bits do not explicitly identify aspecific logical processor by logic processor ID(T0 or T1); instead, they allow a software agent to enable PEBS for subsequent threads of execution on the same logicalprocessor on which the agent is running (“my thread”) or for the other logicalprocessor in the physical package on which the agent is not running (“other thread”).PEBS is supported for only a subset of the at-retirement events: Execution_event,Front_end_event, and Replay_event.
Also, PEBS can be carried out only with twoperformance counters: MSR_IQ_CCCR4 (MSR address 370H) for logical processor 0and MSR_IQ_CCCR5 (MSR address 371H) for logical processor 1.Performance monitoring tools should use a processor affinity mask to bind the kernelmode components that need to modify the ENABLE_PEBS_MY_THR andENABLE_PEBS_OTH_THR bits in the MSR_PEBS_ENABLE MSR to a specific logicalprocessor.
This is to prevent these kernel mode components from migrating betweendifferent logical processors due to OS scheduling.18.16.4 Performance Monitoring EventsAll of the events listed in Table A-5 and A-6 are available in an Intel Xeon processorMP. When Hyper-Threading Technology is active, many performance monitoringevents can be can be qualified by the logical processor ID, which corresponds to bit 018-94 Vol. 3DEBUGGING AND PERFORMANCE MONITORINGof the initial APIC ID.
This allows for counting an event in any or all of the logicalprocessors. However, not all the events have this logic processor specificity, or threadspecificity.Here, each event falls into one of two categories:•Thread specific (TS) — The event can be qualified as occurring on a specificlogical processor.•Thread independent (TI) — The event cannot be qualified as being associatedwith a specific logical processor.Table A-11 gives logical processor specific information (TS or TI) for each of theevents described in Tables A-5 and A-6. If for example, a TS event occurred in logicalprocessor T0, the counting of the event (as shown in Table 18-20) depends only onthe setting of the T0_USR and T0_OS flags in the ESCR being used to set up theevent counter.
The T1_USR and T1_OS flags have no effect on the count.Table 18-20. Effect of Logical Processor and CPL Qualificationfor Logical-Processor-Specific (TS) EventsT1_OS/T1_USR =00T1_OS/T1_USR =01T1_OS/T1_USR =11T1_OS/T1_USR =10T0_OS/T0_USR= 00Zero countCounts while T1in USRCounts while T1in OS or USRCounts while T1in OST0_OS/T0_USR= 01Counts while T0in USRCounts while T0in USR or T1 inUSRCounts while (a)T0 in USR or (b)T1 in OS or (c) T1in USRCounts while (a)T0 in OS or (b) T1in OST0_OS/T0_USR= 11Counts while T0in OS or USRCounts while (a)T0 in OS or (b) T0in USR or (c) T1 inUSRCountsirrespective ofCPL, T0, T1Counts while (a)T0 in OS or (b) orT0 in USR or (c)T1 in OST0_OS/T0_USR= 10Counts T0 in OSCounts T0 in OSor T1 in USRCounts while(a)T0 in Os or (b)T1 in OS or (c) T1in USRCounts while (a)T0 in OS or (b) T1in OSWhen a bit in the event mask field is TI, the effect of specifying bit-0-3 of the associated ESCR are described in Table 15-6.
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