Volume 3B System Programming Guide_ Part 2 (794104), страница 15
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This flag is active only when the compareflag is set.Reserved31 30 2927 26 25 24 2320 19 18 17 16 15Threshold13 12 11ESCRSelect0ReservedReservedEnableReserved: Must be set to 11BCompareComplementEdgeFORCE_OVFOVF_PMICascadeOVF6332ReservedFigure 18-23. Counter Configuration Control Register (CCCR)•FORCE_OVF flag, bit 25 — When set, forces a counter overflow on everycounter increment; when clear, overflow only occurs when the counter actuallyoverflows.•OVF_PMI flag, bit 26 — When set, causes a performance monitor interrupt(PMI) to be generated when the counter overflows occurs; when clear, disablesPMI generation.
Note that the PMI is generated on the next event count after thecounter has overflowed.18-68 Vol. 3DEBUGGING AND PERFORMANCE MONITORING•Cascade flag, bit 30 — When set, enables counting on one counter of a counterpair when its alternate counter in the other the counter pair in the same countergroup overflows (see Section 18.15.2, “Performance Counters,” for furtherdetails); when clear, disables cascading of counters.•OVF flag, bit 31 — Indicates that the counter has overflowed when set.
This flagis a sticky flag that must be explicitly cleared by software.The CCCRs are initialized to all 0s on reset.The events that an enabled performance counter actually counts are selected andfiltered by the following flags and fields in the ESCR and CCCR registers and in thequalification order given:1. The event select and event mask fields in the ESCR select a class of events to becounted and one or more event types within the class, respectively.2. The OS and USR flags in the ESCR selected the privilege levels at which eventswill be counted.3. The ESCR select field of the CCCR selects the ESCR.
Since each counter hasseveral ESCRs associated with it, one ESCR must be chosen to select the classesof events that may be counted.4. The compare and complement flags and the threshold field of the CCCR select anoptional threshold to be used in qualifying an event count.5. The edge flag in the CCCR allows events to be counted only on rising-edge transitions.The qualification order in the above list implies that the filtered output of one “stage”forms the input for the next.
For instance, events filtered using the privilege levelflags can be further qualified by the compare and complement flags and thethreshold field, and an event that matched the threshold criteria, can be further qualified by edge detection.The uses of the flags and fields in the CCCRs are discussed in greater detail in Section18.15.6, “Programming the Performance Counters for Non-Retirement Events.”18.15.4 Debug Store (DS) MechanismThe debug store (DS) mechanism was introduced in the Pentium 4 and Intel Xeonprocessors to allow various types of information to be collected in memory-residentbuffers for use in debugging and tuning programs.
For the Pentium 4 and Intel Xeonprocessors, the DS mechanism is used to collect two types of information: branchrecords and precise event-based sampling (PEBS) records. The availability of the DSmechanism in a processor is indicated with the DS feature flag (bit 21) returned bythe CPUID instruction.See Section 18.6.8, “Branch Trace Store (BTS),” and Section 18.15.8, “Precise EventBased Sampling (PEBS),” for a description of these facilities. Records collected withthe DS mechanism are saved in the DS save area.
See Section 18.15.5, “DS SaveArea.”Vol. 3 18-69DEBUGGING AND PERFORMANCE MONITORING18.15.5 DS Save AreaThe debug store (DS) save area is a software-designated area of memory that isused to collect the following two types of information:•Branch records — When the BTS flag in the MSR_DEBUGCTLA MSR is set, abranch record is stored in the BTS buffer in the DS save area whenever a takenbranch, interrupt, or exception is detected.•PEBS records — When a performance counter is configured for PEBS, a PEBSrecord is stored in the PEBS buffer in the DS save area after the counter overflowoccurs. This record contains the architectural state of the processor (state of the8 general purpose registers, EIP register, and EFLAGS register) at the nextoccurrence of the PEBS event that caused the counter to overflow.
When thestate information has been logged, the counter is automatically reset to apreselected value, and event counting begins again. This feature is available onlyfor a subset of the Pentium 4 and Intel Xeon processors’ performance events.NOTESDS save area and recording mechanism is not available in the SMM.The feature is disabled on transition to the SMM mode. Similarly DSrecording is disabled on the generation of a machine check exceptionand is cleared on processor RESET and INIT. DS recording is availablein real address mode.The BTS and PEBS facilities may not be available on all processors.The availability of these facilities is indicated by theBTS_UNAVAILABLE and PEBS_UNAVAILABLE flags, respectively, inthe IA32_MISC_ENABLE MSR (see Appendix B).The DS save area is divided into three parts (see Figure 18-24): buffer managementarea, branch trace store (BTS) buffer, and PEBS buffer.
The buffer management areais used to define the location and size of the BTS and PEBS buffers. The processorthen uses the buffer management area to keep track of the branch and/or PEBSrecords in their respective buffers and to record the performance counter reset value.The linear address of the first byte of the DS buffer management area is specifiedwith the IA32_DS_AREA MSR.The fields in the buffer management area are as follows:•BTS buffer base — Linear address of the first byte of the BTS buffer.
Thisaddress should point to a natural doubleword boundary.•BTS index — Linear address of the first byte of the next BTS record to be writtento. Initially, this address should be the same as the address in the BTS bufferbase field.•BTS absolute maximum — Linear address of the next byte past the end of theBTS buffer. This address should be a multiple of the BTS record size (12 bytes)plus 1.18-70 Vol. 3DEBUGGING AND PERFORMANCE MONITORING•BTS interrupt threshold — Linear address of the BTS record on which aninterrupt is to be generated. This address must point to an offset from the BTSbuffer base that is a multiple of the BTS record size.
Also, it must be severalrecords short of the BTS absolute maximum address to allow a pending interruptto be handled prior to processor writing the BTS absolute maximum record.•PEBS buffer base — Linear address of the first byte of the PEBS buffer. Thisaddress should point to a natural doubleword boundary.•PEBS index — Linear address of the first byte of the next PEBS record to bewritten to. Initially, this address should be the same as the address in the PEBSbuffer base field.IA32_DS_AREA MSRDS Buffer Management AreaBTS Buffer Base0HBTS Index4HBTS BufferBranch Record 0BTS AbsoluteMaximumBTS InterruptThreshold8HBranch Record 1CHPEBS Buffer Base 10HPEBS IndexPEBS AbsoluteMaximumPEBS InterruptThresholdPEBSCounter ResetReserved14H18HBranch Record n1CH20H24HPEBS Buffer30HPEBS Record 0PEBS Record 1PEBS Record nFigure 18-24. DS Save AreaVol.
3 18-71DEBUGGING AND PERFORMANCE MONITORING•PEBS absolute maximum — Linear address of the next byte past the end of thePEBS buffer. This address should be a multiple of the PEBS record size (40 bytes)plus 1.•PEBS interrupt threshold — Linear address of the PEBS record on which aninterrupt is to be generated.
This address must point to an offset from the PEBSbuffer base that is a multiple of the PEBS record size. Also, it must be severalrecords short of the PEBS absolute maximum address to allow a pendinginterrupt to be handled prior to processor writing the PEBS absolute maximumrecord.•PEBS counter reset value — A 40-bit value that the counter is to be reset toafter state information has collected following counter overflow. This value allowsstate information to be collected after a preset number of events have beencounted.Figures 18-25 shows the structure of a 12-byte branch record in the BTS buffer.
Thefields in each record are as follows:•Last branch from — Linear address of the instruction from which the branch,interrupt, or exception was taken.•Last branch to — Linear address of the branch target or the first instruction inthe interrupt or exception service routine.•Branch predicted — Bit 4 of field indicates whether the branch that was takenwas predicted (set) or not predicted (clear).3140Last Branch From0HLast Branch To4H8HBranch PredictedFigure 18-25. 32-bit Branch Trace Record FormatFigures 18-26 shows the structure of the 40-byte PEBS records. Nominally theregister values are those at the beginning of the instruction that caused the event.However, there are cases where the registers may be logged in a partially modifiedstate.
The linear IP field shows the value in the EIP register translated from an offsetinto the current code segment to a linear address.18-72 Vol. 3DEBUGGING AND PERFORMANCE MONITORING310EFLAGS0HLinear IP4HEAX8HEBXCHECX10HEDX14HESI18HEDI1CHEBP20HESP24HFigure 18-26. PEBS Record Format18.15.5.1 DS Save Area and IA-32e Mode OperationWhen IA-32e mode is active (IA32_EFER.LMA = 1), the structure of the DS save areais shown in Figure 18-27. The organization of each field in IA-32e mode operation issimilar to that of non-IA-32e mode operation. However, each field now stores a64-bit address. The IA32_DS_AREA MSR holds the 64-bit linear address of the firstbyte of the DS buffer management area.Vol.
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