Volume 3B System Programming Guide_ Part 2 (794104), страница 13
Текст из файла (страница 13)
SeeSection 18.5.2.2, “Debug Store (DS) Mechanism,” for guidelines when writing the DSISR.The service routine can query MSR_PERF_GLOBAL_STATUS to determine whichcounter(s) caused of overflow condition. The service routine should clear overflowindicator by writing to MSR_PERF_GLOBAL_OVF_CTL.A comparison of the sequence of requirements to program PEBS for processors basedon Intel Core and Intel NetBurst microarchitectures is listed in Table 18-16.Table 18-16. Requirements to Program PEBSFor Processors based on IntelCore microarchitectureVerify PEBS support ofprocessor/OS18-58 Vol. 3For Processors based on IntelNetBurst microarchitecture• IA32_MISC_ENABLES.EMON_AVAILABE (bit 7) is set.• IA32_MISC_ENABLES.PEBS_UNAVAILABE (bit 12) is clear.DEBUGGING AND PERFORMANCE MONITORINGTable 18-16.
Requirements to Program PEBS (Contd.)Ensure counters are indisabledFor Processors based on IntelCore microarchitectureFor Processors based on IntelNetBurst microarchitectureOn initial set up or changing eventconfigurations, writeMSR_PERF_GLOBAL_CTRL MSR(0x38F) with 0.OptionalOn subsequent entries:• Clear all counters if “CounterFreeze on PMI“ is not enabled.• If IA32_DebugCTL.Freeze isenabled, counters areautomatically disabled.Counters MUST be stopped beforewriting.1Disable PEBS.Clear ENABLE PMC0 bit inIA32_PEBS_ENABLE MSR(0x3F1).OptionalCheck overflowconditions.CheckMSR_PERF_GLOBAL_STATUS MSR(0x 38E) handle any overflowconditions.Check OVF flag of each CCCR foroverflow conditionClear overflow status.ClearMSR_PERF_GLOBAL_STATUS MSR(0x 38E) usingIA32_PERF_GLOBAL_OVF_CTRLMSR (0x390).Clear OVF flag of each CCCR.Write “sample-after“values.Configure the counter(s) with the sample after value.Configure specific counterconfiguration MSR.• Set local enable bit 22 - 1.• Do NOT set local counterPMI/INT bit, bit 20 - 0.• Event programmed must bePEBS capable.Allocate buffer for PEBSstates.Allocate a buffer in memory for the precise information.Program theIA32_DS_AREA MSR.Program the IA32_DS_AREA MSR.Configure the PEBS buffermanagement records.Configure the PEBS buffer management records in the DS buffermanagement area.• Set appropriate OVF_PMI bits 1.• Only CCCR forMSR_IQ_COUNTER4 supportPEBS.Vol.
3 18-59DEBUGGING AND PERFORMANCE MONITORINGTable 18-16. Requirements to Program PEBS (Contd.)For Processors based on IntelCore microarchitectureFor Processors based on IntelNetBurst microarchitectureConfigure/Enable PEBS.Set Enable PMC0 bit inIA32_PEBS_ENABLE MSR(0x3F1).Configure MSR_PEBS_ENABLE,MSR_PEBS_MATRIX_VERT andMSR_PEBS_MATRIX_HORZ asneeded.Enable counters.Set Enable bits inMSR_PERF_GLOBAL_CTRL MSR(0x38F).Set each CCCR enable bit 12 - 1.NOTES:1.
Counters read while enabled are not guaranteed to be precise with event counts that occur in timing proximity to the RDMSR.18.15PERFORMANCE MONITORING (PROCESSORSBASED ON INTEL NETBURST MICROARCHITECTURE)The performance monitoring mechanism provided in Pentium 4 and Intel Xeonprocessors is different from that provided in the P6 family and Pentium processors.While the general concept of selecting, filtering, counting, and reading performanceevents through the WRMSR, RDMSR, and RDPMC instructions is unchanged, thesetup mechanism and MSR layouts are incompatible with the P6 family and Pentiumprocessor mechanisms.
Also, the RDPMC instruction has been enhanced to read thethe additional performance counters provided in the Pentium 4 and Intel Xeonprocessors and to allow faster reading of counters.The event monitoring mechanism provided with the Pentium 4 and Intel Xeonprocessors (based on Intel NetBurst microarchitecture) consists of the following facilities:•The IA32_MISC_ENABLE MSR, which indicates the availability in an Intel 64 orIA-32 processor of the performance monitoring and precise event-basedsampling (PEBS) facilities.•Event selection control (ESCR) MSRs for selecting events to be monitored withspecific performance counters. The number available differs by family and model(43 to 45).••18 performance counter MSRs for counting events.••A debug store (DS) save area in memory for storing PEBS records.18 counter configuration control (CCCR) MSRs, with one CCCR associated witheach performance counter.
CCCRs sets up an associated performance counter fora specific method of counting.The IA32_DS_AREA MSR, which establishes the location of the DS save area.18-60 Vol. 3DEBUGGING AND PERFORMANCE MONITORING•The debug store (DS) feature flag (bit 21) returned by the CPUID instruction,which indicates the availability of the DS mechanism.•The MSR_PEBS_ENABLE MSR, which enables the PEBS facilities and replaytagging used in at-retirement event counting.•A set of predefined events and event metrics that simplify the setting up of theperformance counters to count specific events.Table 18-17 lists the performance counters and their associated CCCRs, along withthe ESCRs that select events to be counted for each performance counter. Predefinedevent metrics and events are listed in Appendix A, “Performance-Monitoring Events.”Table 18-17.
Performance Counter MSRs and Associated CCCR andESCR MSRs (Pentium 4 and Intel Xeon Processors)CounterCCCRESCRNameNo.AddrNameAddrNameNo. AddrMSR_BPU_COUNTER00300HMSR_BPU_CCCR0360HMSR_BSU_ESCR0MSR_FSB_ESCR0MSR_MOB_ESCR0MSR_PMH_ESCR0MSR_BPU_ESCR0MSR_IS_ESCR0MSR_ITLB_ESCR0MSR_IX_ESCR0762401353A0H3A2H3AAH3ACH3B2H3B4H3B6H3C8HMSR_BPU_COUNTER11301HMSR_BPU_CCCR1361HMSR_BSU_ESCR0MSR_FSB_ESCR0MSR_MOB_ESCR0MSR_PMH_ESCR0MSR_BPU_ESCR0MSR_IS_ESCR0MSR_ITLB_ESCR0MSR_IX_ESCR0762401353A0H3A2H3AAH3ACH3B2H3B4H3B6H3C8HMSR_BPU_COUNTER22302HMSR_BPU_CCCR2362HMSR_BSU_ESCR1MSR_FSB_ESCR1MSR_MOB_ESCR1MSR_PMH_ESCR1MSR_BPU_ESCR1MSR_IS_ESCR1MSR_ITLB_ESCR1MSR_IX_ESCR1762401353A1H3A3H3ABH3ADH3B3H3B5H3B7H3C9HMSR_BPU_COUNTER33303HMSR_BPU_CCCR3363HMSR_BSU_ESCR1MSR_FSB_ESCR1MSR_MOB_ESCR1MSR_PMH_ESCR1MSR_BPU_ESCR1MSR_IS_ESCR1MSR_ITLB_ESCR1MSR_IX_ESCR1762401353A1H3A3H3ABH3ADH3B3H3B5H3B7H3C9HVol.
3 18-61DEBUGGING AND PERFORMANCE MONITORINGTable 18-17. Performance Counter MSRs and Associated CCCR andESCR MSRs (Pentium 4 and Intel Xeon Processors) (Contd.)CounterCCCRESCRNameNo.AddrNameAddrNameNo. AddrMSR_MS_COUNTER04304HMSR_MS_CCCR0364HMSR_MS_ESCR0MSR_TBPU_ESCR0MSR_TC_ESCR00213C0H3C2H3C4HMSR_MS_COUNTER15305HMSR_MS_CCCR1365HMSR_MS_ESCR0MSR_TBPU_ESCR0MSR_TC_ESCR00213C0H3C2H3C4HMSR_MS_COUNTER26306HMSR_MS_CCCR2366HMSR_MS_ESCR1MSR_TBPU_ESCR1MSR_TC_ESCR10213C1H3C3H3C5HMSR_MS_COUNTER37307HMSR_MS_CCCR3367HMSR_MS_ESCR1MSR_TBPU_ESCR1MSR_TC_ESCR10213C1H3C3H3C5HMSR_FLAME_COUNTER08308HMSR_FLAME_CCCR0368HMSR_FIRM_ESCR0MSR_FLAME_ESCR0MSR_DAC_ESCR0MSR_SAAT_ESCR0MSR_U2L_ESCR0105233A4H3A6H3A8H3AEH3B0HMSR_FLAME_COUNTER19309HMSR_FLAME_CCCR1369HMSR_FIRM_ESCR0MSR_FLAME_ESCR0MSR_DAC_ESCR0MSR_SAAT_ESCR0MSR_U2L_ESCR0105233A4H3A6H3A8H3AEH3B0HMSR_FLAME_COUNTER21030AHMSR_FLAME_CCCR236AHMSR_FIRM_ESCR1MSR_FLAME_ESCR1MSR_DAC_ESCR1MSR_SAAT_ESCR1MSR_U2L_ESCR1105233A5H3A7H3A9H3AFH3B1HMSR_FLAME_COUNTER31130BHMSR_FLAME_CCCR336BHMSR_FIRM_ESCR1MSR_FLAME_ESCR1MSR_DAC_ESCR1MSR_SAAT_ESCR1MSR_U2L_ESCR1105233A5H3A7H3A9H3AFH3B1HMSR_IQ_COUNTER01230CHMSR_IQ_CCCR036CHMSR_CRU_ESCR0MSR_CRU_ESCR2MSR_CRU_ESCR4MSR_IQ_ESCR01MSR_RAT_ESCR0MSR_SSU_ESCR0MSR_ALF_ESCR045602313B8H3CCH3E0H3BAH3BCH3BEH3CAHMSR_IQ_COUNTER11330DHMSR_IQ_CCCR136DHMSR_CRU_ESCR0MSR_CRU_ESCR2MSR_CRU_ESCR4MSR_IQ_ESCR01MSR_RAT_ESCR0MSR_SSU_ESCR0MSR_ALF_ESCR045602313B8H3CCH3E0H3BAH3BCH3BEH3CAH18-62 Vol.
3DEBUGGING AND PERFORMANCE MONITORINGTable 18-17. Performance Counter MSRs and Associated CCCR andESCR MSRs (Pentium 4 and Intel Xeon Processors) (Contd.)CounterCCCRESCRNameNo.AddrNameAddrNameNo. AddrMSR_IQ_COUNTER21430EHMSR_IQ_CCCR236EHMSR_CRU_ESCR1MSR_CRU_ESCR3MSR_CRU_ESCR5MSR_IQ_ESCR11MSR_RAT_ESCR1MSR_ALF_ESCR14560213B9H3CDH3E1H3BBH3BDH3CBHMSR_IQ_COUNTER31530FHMSR_IQ_CCCR336FHMSR_CRU_ESCR1MSR_CRU_ESCR3MSR_CRU_ESCR5MSR_IQ_ESCR11MSR_RAT_ESCR1MSR_ALF_ESCR14563B9H3CDH3E1H3BBH3BDH3CBH210MSR_IQ_COUNTER416310HMSR_IQ_CCCR4370HMSR_CRU_ESCR0MSR_CRU_ESCR2MSR_CRU_ESCR4MSR_IQ_ESCR01MSR_RAT_ESCR0MSR_SSU_ESCR0MSR_ALF_ESCR045602313B8H3CCH3E0H3BAH3BCH3BEH3CAHMSR_IQ_COUNTER517311HMSR_IQ_CCCR5371HMSR_CRU_ESCR1MSR_CRU_ESCR3MSR_CRU_ESCR5MSR_IQ_ESCR11MSR_RAT_ESCR1MSR_ALF_ESCR14560213B9H3CDH3E1H3BBH3BDH3CBHNOTES:1.
MSR_IQ_ESCR0 and MSR_IQ_ESCR1 are available only on early processor builds (family 0FH, models 01H-02H). These MSRs are not available on later versions.The types of events that can be counted with these performance monitoring facilitiesare divided into two classes: non-retirement events and at-retirement events.•Non-retirement events (see Table A-5) are events that occur any time duringinstruction execution (such as bus transactions or cache transactions).•At-retirement events (see Table A-6) are events that are counted at theretirement stage of instruction execution, which allows finer granularity incounting events and capturing machine state.The at-retirement counting mechanism includes facilities for tagging μops thathave encountered a particular performance event during instruction execution.Tagging allows events to be sorted between those that occurred on an executionpath that resulted in architectural state being committed at retirement as well asevents that occurred on an execution path where the results were eventuallycancelled and never committed to architectural state (such as, the execution of amispredicted branch).Vol.
3 18-63DEBUGGING AND PERFORMANCE MONITORINGThe Pentium 4 and Intel Xeon processor performance monitoring facilities supportthe three usage models described below. The first two models can be used to countboth non-retirement and at-retirement events; the third model is used to count asubset of at-retirement events:•Event counting — A performance counter is configured to count one or moretypes of events. While the counter is counting, software reads the counter atselected intervals to determine the number of events that have been countedbetween the intervals.•Non-precise event-based sampling — A performance counter is configured tocount one or more types of events and to generate an interrupt when itoverflows.
To trigger an overflow, the counter is preset to a modulus value thatwill cause the counter to overflow after a specific number of events have beencounted.When the counter overflows, the processor generates a performance monitoringinterrupt (PMI). The interrupt service routine for the PMI then records the returninstruction pointer (RIP), resets the modulus, and restarts the counter. Codeperformance can be analyzed by examining the distribution of RIPs with a toollike the VTune™ Performance Analyzer.•Precise event-based sampling (PEBS) — This type of performancemonitoring is similar to non-precise event-based sampling, except that amemory buffer is used to save a record of the architectural state of the processorwhenever the counter overflows.
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