Volume 3B System Programming Guide_ Part 2 (794104), страница 9
Текст из файла (страница 9)
The counter’s architecture includes thefollowing components:•TSC flag — A feature bit that indicates the availability of the time-stamp counter.The counter is available in an if the function CPUID.1:EDX.TSC[bit 4] = 1.•IA32_TIME_STAMP_COUNTER MSR (called TSC MSR in P6 family andPentium processors) — The MSR used as the counter.••RDTSC instruction — An instruction used to read the time-stamp counter.TSD flag — A control register flag is used to enable or disable the time-stampcounter (enabled if CR4.TSD[bit 2] = 1).The time-stamp counter (as implemented in the P6 family, Pentium, Pentium M,Pentium 4, Intel Xeon, Intel Core Solo and Intel Core Duo processors) is a 64-bitcounter that is set to 0 following a RESET of the processor.
Following a RESET, thecounter increments even when the processor is halted by the HLT instruction or theexternal STPCLK# pin. Note that the assertion of the external DPSLP# pin may causethe time-stamp counter to stop.Processor families increment the time-stamp counter differently:•For Pentium M processors (family [06H], models [09H, 0DH]); for Pentium 4processors, Intel Xeon processors (family [0FH], models [00H, 01H, or 02H]);and for P6 family processors: the time-stamp counter increments with everyinternal processor clock cycle.The internal processor clock cycle is determined by the current core-clock to busclock ratio. Intel® SpeedStep® technology transitions may also impact theprocessor clock.•For Pentium 4 processors, Intel Xeon processors (family [0FH], models [03H andhigher]); for Intel Core Solo and Intel Core Duo processors (family [06H], model[0EH]); for the Intel Xeon processor 5100 series and Intel Core 2 Duo processors(family [06H], model [0FH]): the time-stamp counter increments at a constantVol.
3 18-37DEBUGGING AND PERFORMANCE MONITORINGrate. That rate may be set by the maximum core-clock to bus-clock ratio of theprocessor or may be set by the maximum resolved frequency at which theprocessor is booted. The maximum resolved frequency may differ from themaximum qualified frequency of the processor, see Section 18.17.5 for moredetail.The specific processor configuration determines the behavior.
Constant TSCbehavior ensures that the duration of each clock tick is uniform and supports theuse of the TSC as a wall clock timer even if the processor core changes frequency.This is the architectural behavior moving forward.NOTETo determine average processor clock frequency, Intel recommendsthe use of EMON logic to count processor core clocks over the periodof time for which the average is required. See Section 18.17,“Counting Clocks,” and Appendix A, “PerformanceMonitoring Events,” for more information.The RDTSC instruction reads the time-stamp counter and is guaranteed to return amonotonically increasing unique value whenever executed, except for a 64-bitcounter wraparound.
Intel guarantees that the time-stamp counter will not wraparound within 10 years after being reset. The period for counter wrap is longer forPentium 4, Intel Xeon, P6 family, and Pentium processors.Normally, the RDTSC instruction can be executed by programs and proceduresrunning at any privilege level and in virtual-8086 mode.
The TSD flag allows use ofthis instruction to be restricted to programs and procedures running at privilege level0. A secure operating system would set the TSD flag during system initialization todisable user access to the time-stamp counter. An operating system that disablesuser access to the time-stamp counter should emulate the instruction through auser-accessible programming interface.The RDTSC instruction is not serializing or ordered with other instructions.
It does notnecessarily wait until all previous instructions have been executed before reading thecounter. Similarly, subsequent instructions may begin execution before the RDTSCinstruction operation is performed.The RDMSR and WRMSR instructions read and write the time-stamp counter, treatingthe time-stamp counter as an ordinary MSR (address 10H). In the Pentium 4, IntelXeon, and P6 family processors, all 64-bits of the time-stamp counter are read usingRDMSR (just as with RDTSC). When WRMSR is used to write the time-stamp counteron processors before family [0FH], models [03H, 04H]: only the low-order 32-bits ofthe time-stamp counter can be written (the high-order 32 bits are cleared to 0).
Forfamily [0FH], models [03H, 04H, 06H]; for family [06H]], model [0EH, 0FH]: all 64bits are writable.18-38 Vol. 3DEBUGGING AND PERFORMANCE MONITORING18.11PERFORMANCE MONITORING OVERVIEWPerformance monitoring was introduced in the Pentium processor with a set ofmodel-specific performance-monitoring counter MSRs. These counters permit selection of processor performance parameters to be monitored and measured. The information obtained from these counters can be used for tuning system and compilerperformance.In Intel P6 family of processors, the performance monitoring mechanism wasenhanced to permit a wider selection of events to be monitored and to allow greatercontrol events to be monitored. Next, Pentium 4 and Intel Xeon processors introduced a new performance monitoring mechanism and new set of performanceevents.The performance monitoring mechanisms and performance events defined for thePentium, P6 family, Pentium 4, and Intel Xeon processors are not architectural.
Theyare all model specific (not compatible among processor families). Intel Core Solo andIntel Core Duo processors support a set of architectural performance events and aset of non-architectural performance events. Processors based Intel Core microarchitecture support enhanced architectural performance events and non-architecturalperformance events.Starting with Intel Core Solo and Intel Core Duo processors, there are two classes ofperformance monitoring capabilities. The first class supports events for monitoringperformance using counting or sampling usage.
These events are non-architecturaland vary from one processor model to another. They are similar to those available inPentium M processors. These non-architectural performance monitoring events arespecific to the microarchitecture and may change with enhancements. They arediscussed in Section 18.13, “Performance Monitoring (Intel® Core™ Solo and Intel®Core™ Duo Processors).” Non-architectural events for a given microarchitecture cannot be enumerated using CPUID; and they are listed in Appendix A, “PerformanceMonitoring Events.”The second class of performance monitoring capabilities is referred to as architectural performance monitoring.
This class supports the same counting and samplingusages, with a smaller set of available events. The visible behavior of architecturalperformance events is consistent across processor implementations. Availability ofarchitectural performance monitoring capabilities is enumerated using theCPUID.0AH. These events are discussed in Section 18.12.See also:— Section 18.12, “Architectural Performance Monitoring”— Section 18.13, “Performance Monitoring (Intel® Core™ Solo and Intel® Core™Duo Processors)”— Section 18.14, “Performance Monitoring (Processors based on Intel® Core™Microarchitecture)”— Section 18.15, “Performance Monitoring (Processors Based on Intel NetBurstmicroarchitecture)”Vol.
3 18-39DEBUGGING AND PERFORMANCE MONITORING— Section 18.16, “Performance Monitoring and Hyper-Threading Technology”— Section 18.18, “Performance Monitoring and Dual-Core Technology”— Section 18.19, “Performance Monitoring on 64-bit Intel Xeon Processor MPwith Up to 8-MByte L3 Cache”— Section 18.21, “Performance Monitoring (P6 Family Processor)”— Section 18.22, “Performance Monitoring (Pentium Processors)”18.12ARCHITECTURAL PERFORMANCE MONITORINGPerformance monitoring events are architectural when they behave consistentlyacross microarchitectures. Intel Core Solo and Intel Core Duo processors introducedarchitectural performance monitoring.
The feature provides a mechanism for software to enumerate performance events and provides configuration and countingfacilities for events.Architectural performance monitoring does allow for enhancement across processorimplementations. The CPUID.0AH leaf provides version ID for each enhancement.Intel Core Solo and Intel Core Duo processors support base level functionality identified by version ID of 1.
Processors based on Intel Core microarchitecture support, ata minimum, the base level functionality of architectural performance monitoring.Intel Core 2 Duo processor T 7700 and newer processors based on Intel Coremicroarchitecture support both the base level functionality and enhanced architectural performance monitoring identified by version ID of 2.18.12.1 Architectural Performance Monitoring Version 1Configuring an architectural performance monitoring event involves programmingperformance event select registers.
There are a finite number of performance eventselect MSRs (IA32_PERFEVTSELx MSRs). The result of a performance monitoringevent is reported in a performance monitoring counter (IA32_PMCx MSR). Performance monitoring counters are paired with performance monitoring select registers.Performance monitoring select registers and counters are architectural in thefollowing respects:••Bit field layout of IA32_PERFEVTSELx is consistent across microarchitectures.••Addresses of IA32_PMC MSRs remain the same across microarchitectures.Addresses of IA32_PERFEVTSELx MSRs remain the same across microarchitectures.Each logical processor has its own set of IA32_PERFEVTSELx and IA32_PMCxMSRs.
Configuration facilities and counters are not shared between logicalprocessors sharing a processor core.18-40 Vol. 3DEBUGGING AND PERFORMANCE MONITORINGArchitectural performance monitoring provides a CPUID mechanism for enumeratingthe following information:•Number of performance monitoring counters available in a logical processor(each IA32_PERFEVTSELx MSR is paired to the corresponding IA32_PMCx MSR)••Number of bits supported in each IA32_PMCxNumber of architectural performance monitoring events supported in a logicalprocessorSoftware can use CPUID to discover architectural performance monitoring availability(CPUID.0AH).
The architectural performance monitoring leaf provides an identifiercorresponding to the version number of architectural performance monitoring available in the processor.The version identifier is retrieved by querying CPUID.0AH:EAX[bits 7:0] (seeChapter 3, “Instruction Set Reference, A-M,” in the Intel® 64 and IA-32 ArchitecturesSoftware Developer’s Manual, Volume 2A). If the version identifier is greater thanzero, architectural performance monitoring capability is supported. Software queriesthe CPUID.0AH for the version identifier first; it then analyzes the value returned inCPUID.0AH.EAX, CPUID.0AH.EBX to determine the facilities available.In the initial implementation of architectural performance monitoring; software candetermine how many IA32_PERFEVTSELx/ IA32_PMCx MSR pairs are supported percore, the bit-width of PMC, and the number of architectural performance monitoringevents available.18.12.1.1 Architectural Performance Monitoring Version 1 FacilitiesArchitectural performance monitoring facilities include a set of performance monitoring counters and performance event select registers.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
