Volume 3B System Programming Guide_ Part 2 (794104), страница 5
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Fields in the buffermanagement area of a DS save area are described in Section 18.15.5.The format of a branch trace record and a PEBS record are the same as the 64-bitrecord formats shown in Figures 18-28 and Figures 18-29, with the exception thatthe branch predicted bit is not supported by Intel Core microarchitecture. The 64-bitrecord formats for BTS and PEBS apply to DS save area for all operating modes.The procedures used to program IA32_DEBUG_CTRL MSR to set up a BTS buffer or aCPL-qualified BTS are described in Section 18.6.8.3 and Section 18.6.8.4.Vol. 3 18-17DEBUGGING AND PERFORMANCE MONITORINGRequired elements for writing a DS interrupt service routine are largely the same asthose described in Section 18.6.8.5.
However, instead of re-enabling counting usingCCCRs like on processors based on Intel NetBurst® microarchitecture, a DS interruptservice routine on processors based on Intel Core microarchitecture should:•Re-enable the enable bits in MSR_PERF_GLOBAL_CTRL MSR if it is servicing anoverflow PMI due to PEBS.•Clear overflow indications by writing to MSR_PERF_GLOBAL_OVF_CTRL when acounting configuration is changed. This includes bit 62 (ClrOvfBuffer) and theoverflow indication of counters used in either PEBS or general-purpose counting(specifically: bits 0 or 1; see Figures 18-20).18.6LAST BRANCH, INTERRUPT, AND EXCEPTIONRECORDING (PROCESSORS BASED ON INTELNETBURST® MICROARCHITECTURE)Pentium 4 and Intel Xeon processors based on Intel NetBurst microarchitectureprovide the following methods for recording taken branches, interrupts and exceptions:•Store branch records in the last branch record (LBR) stack MSRs for the mostrecent taken branches, interrupts, and/or exceptions in MSRs.
A branch recordconsist of a branch-from and a branch-to instruction address.•Send the branch records out on the system bus as branch trace messages(BTMs).•Log BTMs in a memory-resident branch trace store (BTS) buffer.To support these functions, the processor provides the following MSRs:•MSR_DEBUGCTLA MSR — Enables last branch, interrupt, and exceptionrecording; single-stepping on taken branches; branch trace messages (BTMs);and branch trace store (BTS). This register is named DebugCtlMSR in the P6family processors.•Debug store (DS) feature flag (CPUID.1:EDX.DS[bit 21]) — Indicates thatthe processor provides the debug store (DS) mechanism, which allows BTMs tobe stored in a memory-resident BTS buffer.•CPL-qualified debug store (DS) feature flag (CPUID.1:ECX.DS-CPL[bit4]) — Indicates that the processor provides a CPL-qualified debug store (DS)mechanism, which allows software to selectively skip storing BTMs, according tospecified current privilege level settings, into a memory-resident BTS buffer.•IA32_MISC_ENABLE MSR — Indicates that the processor provides the BTSfacilities.•Last branch record (LBR) stack — The LBR stack is a circular stack thatconsists of four MSRs (MSR_LASTBRANCH_0 through MSR_LASTBRANCH_3) forthe Pentium 4 and Intel Xeon processor family [CPUID family 0FH, models 0H-18-18 Vol.
3DEBUGGING AND PERFORMANCE MONITORING02H]. The LBR stack consists of 16 MSR pairs (MSR_LASTBRANCH_0_FROM_LIPthrough MSR_LASTBRANCH_15_FROM_LIP and MSR_LASTBRANCH_0_TO_LIPthrough MSR_LASTBRANCH_15_TO_LIP) for the Pentium 4 and Intel Xeonprocessor family [CPUID family 0FH, model 03H].•Last branch record top-of-stack (TOS) pointer — The TOS Pointer MSRcontains a 2-bit pointer (0-3) to the MSR in the LBR stack that contains the mostrecent branch, interrupt, or exception recorded for the Pentium 4 and Intel Xeonprocessor family [CPUID family 0FH, models 0H-02H].
This pointer becomes a4-bit pointer (0-15) for the Pentium 4 and Intel Xeon processor family [CPUIDfamily 0FH, model 03H]. See also: Table 18-3, Figure 18-5, and Section 18.6.3,“LBR Stack.”•Last exception record — See Section 18.6.7, “Last Exception Records.”18.6.1CPL-Qualified Last Branch Recording MechanismCPL-qualified last branch recording mechanism is available to a subset of Intel 64 andIA-32 processors that support the last branch recording mechanism.
Softwaresupports the CPL-qualified last branch recording mechanism ifCPUID.01H:ECX[bit 4] = 1.The CPL-qualified last branch recording mechanism is similar to that described inSections 18.6, 18.6.2, and 18.6.8. It also sends branch records out on the systembus as branch trace messages (BTMs). But system software can selectively specifyCPL qualification to not store BTMs associated with a specified privilege level. Two bitfields, BTS_OFF_USR and BTS_OFF_OS, are provided in the debug control register tospecify the CPL of BTMs that will not be logged in the BTS buffer.Table 18-3.
LBR MSR Stack Structure for the Pentium® 4 andthe Intel® Xeon® Processor FamilyLBR MSRs for Family 0FH, Models 0H-02H;MSRs at locations 1DBH-1DEH.Decimal Value of TOS Pointer inMSR_LASTBRANCH_TOS (bits 0-1)MSR_LASTBRANCH_00MSR_LASTBRANCH_11MSR_LASTBRANCH_22MSR_LASTBRANCH_33LBR MSRs for Family 0FH, Models; MSRs atlocations 680H-68FH.Decimal Value of TOS Pointer inMSR_LASTBRANCH_TOS (bits 0-3MSR_LASTBRANCH_0_FROM_LIP0MSR_LASTBRANCH_1_FROM_LIP1MSR_LASTBRANCH_2_FROM_LIP2Vol. 3 18-19DEBUGGING AND PERFORMANCE MONITORINGTable 18-3.
LBR MSR Stack Structure for the Pentium® 4 andthe Intel® Xeon® Processor Family (Contd.)LBR MSRs for Family 0FH, Models; MSRs atlocations 680H-68FH.Decimal Value of TOS Pointer inMSR_LASTBRANCH_TOS (bits 0-3)MSR_LASTBRANCH_3_FROM_LIP3MSR_LASTBRANCH_4_FROM_LIP4MSR_LASTBRANCH_5_FROM_LIP5MSR_LASTBRANCH_6_FROM_LIP6MSR_LASTBRANCH_7_FROM_LIP7MSR_LASTBRANCH_8_FROM_LIP8MSR_LASTBRANCH_9_FROM_LIP9MSR_LASTBRANCH_10_FROM_LIP10MSR_LASTBRANCH_11_FROM_LIP11MSR_LASTBRANCH_12_FROM_LIP12MSR_LASTBRANCH_13_FROM_LIP13MSR_LASTBRANCH_14_FROM_LIP14MSR_LASTBRANCH_15_FROM_LIP15LBR MSRs for Family 0FH, Model 03H; MSRsat locations 6C0H-6CFH.MSR_LASTBRANCH_0_TO_LIP0MSR_LASTBRANCH_1_TO_LIP1MSR_LASTBRANCH_2_TO_LIP2MSR_LASTBRANCH_3_TO_LIP3MSR_LASTBRANCH_4_TO_LIP4MSR_LASTBRANCH_5_TO_LIP5MSR_LASTBRANCH_6_TO_LIP6MSR_LASTBRANCH_7_TO_LIP7MSR_LASTBRANCH_8_TO_LIP8MSR_LASTBRANCH_9_TO_LIP9MSR_LASTBRANCH_10_TO_LIP10MSR_LASTBRANCH_11_TO_LIP11MSR_LASTBRANCH_12_TO_LIP12MSR_LASTBRANCH_13_TO_LIP13MSR_LASTBRANCH_14_TO_LIP14MSR_LASTBRANCH_15_TO_LIP1518-20 Vol.
3DEBUGGING AND PERFORMANCE MONITORINGNOTEThe initial implementation of BTS_OFF_USR and BTS_OFF_OS inMSR_DEBUGCTLA is shown in Figure 18-5. The BTS_OFF_USR andBTS_OFF_OS fields may be implemented on other model-specificdebug control register at different locations.The following sections describe the MSR_DEBUGCTLA MSR and the various lastbranch recording mechanisms. See Appendix B, “Model-Specific Registers (MSRs),”for a detailed description of each of the last branch recording MSRs.18.6.2MSR_DEBUGCTLA MSRThe MSR_DEBUGCTLA MSR enables and disables the various last branch recordingmechanisms described in the previous section.
This register can be written to usingthe WRMSR instruction, when operating at privilege level 0 or when in real-addressmode. A protected-mode operating system procedure is required to provide useraccess to this register. Figure 18-5 shows the flags in the MSR_DEBUGCTLA MSR.The functions of these flags are as follows:•LBR (last branch/interrupt/exception) flag (bit 0) — When set, theprocessor records a running trace of the most recent branches, interrupts, and/orexceptions taken by the processor (prior to a debug exception being generated)in the last branch record (LBR) stack. Each branch, interrupt, or exception isrecorded as a 64-bit branch record. The processor clears this flag whenever adebug exception is generated (for example, when an instruction or databreakpoint or a single-step trap occurs).
See Section 18.6.3, “LBR Stack.”•BTF (single-step on branches) flag (bit 1) — When set, the processor treatsthe TF flag in the EFLAGS register as a “single-step on branches” flag rather thana “single-step on instructions” flag. This mechanism allows single-stepping theprocessor on taken branches, interrupts, and exceptions. See Section 18.6.5,“Single-Stepping on Branches, Exceptions, and Interrupts.”•TR (trace message enable) flag (bit 2) — When set, branch trace messagesare enabled. Thereafter, when the processor detects a taken branch, interrupt, orexception, it sends the branch record out on the system bus as a branch tracemessage (BTM).
See Section 18.6.6, “Branch Trace Messages.”Vol. 3 18-21DEBUGGING AND PERFORMANCE MONITORING317 6 5 4 3 2 1 0ReservedBTS_OFF_USR — Disable storing non-CPL_0 BTSBTS_OFF_OS — Disable storing CPL_0 BTSBTINT — Branch trace interruptBTS — Branch trace storeTR — Trace messages enableBTF — Single-step on branchesLBR — Last branch/interrupt/exceptionFigure 18-5.
MSR_DEBUGCTLA MSR for Pentium 4 and Intel Xeon Processors•BTS (branch trace store) flag (bit 3) — When set, enables the BTS facilities tolog BTMs to a memory-resident BTS buffer that is part of the DS save area. SeeSection 18.15.5, “DS Save Area.”•BTINT (branch trace interrupt) flag (bits 4) — When set, the BTS facilitiesgenerate an interrupt when the BTS buffer is full. When clear, BTMs are logged tothe BTS buffer in a circular fashion.
See Section 18.6.8, “Branch Trace Store (BTS).”•BTS_OFF_OS (disable ring 0 branch trace store) flag (bit 5) — When set,enables the BTS facilities to skip logging CPL_0 BTMs to the memory-residentBTS buffer. See Section 18.6.1, “CPL-Qualified Last Branch RecordingMechanism.”•BTS_OFF_USR (disable ring 0 branch trace store) flag (bit 6) — When set,enables the BTS facilities to skip logging non-CPL_0 BTMs to the memoryresident BTS buffer.
See Section 18.6.1, “CPL-Qualified Last Branch RecordingMechanism.”18.6.3LBR StackThe LBR stack is made up of LBR MSRs that are treated by the processor as a circularstack. The TOS pointer (MSR_LASTBRANCH_TOS MSR) points to the LBR MSR (orLBR MSR pair) that contains the most recent (last) branch record placed on the stack.Prior to placing a new branch record on the stack, the TOS is incremented by 1. Whenthe TOS pointer reaches it maximum value, it wraps around to 0. See Table 18-3 andFigure 18-5.The registers in the LBR MSR stack and the MSR_LASTBRANCH_TOS MSR are readonly and can be read using the RDMSR instruction.Figure 18-6 shows the layout of a branch record in an LBR MSR (or MSR pair).
Eachbranch record consists of two linear addresses, which represent the “from” and “to”18-22 Vol. 3DEBUGGING AND PERFORMANCE MONITORINGinstruction pointers for a branch, interrupt, or exception. The contents of the fromand to addresses differ, depending on the source of the branch:•Taken branch — If the record is for a taken branch, the “from” address is theaddress of the branch instruction and the “to” address is the target instruction ofthe branch.•Interrupt — If the record is for an interrupt, the “from” address the returninstruction pointer (RIP) saved for the interrupt and the “to” address is theaddress of the first instruction in the interrupt handler routine. The RIP is thelinear address of the next instruction to be executed upon returning from theinterrupt handler.•Exception — If the record is for an exception, the “from” address is the linearaddress of the instruction that caused the exception to be generated and the “to”address is the address of the first instruction in the exception handler routine.CPUID Family 0FH, Models 0H-02HMSR_LASTBRANCH_0 through MSR_LASTBRANCH_363032 - 31From Linear AddressTo Linear AddressCPUID Family 0FH, Model 03H-04HMSR_LASTBRANCH_0_FROM_LIP through MSR_LASTBRANCH_15_FROM_LIP032 - 3163ReservedFrom Linear AddressMSR_LASTBRANCH_0_TO_LIP through MSR_LASTBRANCH_15_TO_LIP63032 - 31ReservedTo Linear AddressFigure 18-6.
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