Volume 3B System Programming Guide_ Part 2 (794104), страница 7
Текст из файла (страница 7)
The BTS flag determines whether theBTMs are sent out on the system bus (clear) or stored in the BTS buffer (set). BTMscannot be simultaneously sent to the system bus and logged in the BTS buffer. TheBTINT flag enables the generation of an interrupt when the BTS buffer is full. Whenthis flag is clear, the BTS buffer is a circular buffer.Vol. 3 18-27DEBUGGING AND PERFORMANCE MONITORINGTable 18-4. MSR_DEBUGCTLA, IA32_DEBUGCTL, MSR_DEBUGCLTBFlag EncodingsTRBTSBTINTDescription0XXBranch trace messages (BTMs) off10XGenerate BTMs110Store BTMs in the BTS buffer, used here as a circular buffer111Store BTMs in the BTS buffer, and generate an interrupt whenthe buffer is nearly fullThe following procedure describes how to set up a Pentium 4 or Intel Xeon processorto collect branch records in the BTS buffer in the DS save area:1.
Place values in the BTS buffer base, BTS index, BTS absolute maximum, and BTSinterrupt threshold fields of the DS buffer management area to set up the BTSbuffer in memory.2. Set the TR and BTS flags in the MSR_DEBUGCTLA MSR (or IA32_DEBUGCTL forIntel Core Solo and Intel Core Duo processors; or MSR_DEBUGCTLB for PentiumM processors).3.
Either clear the BTINT flag in the MSR_DEBUGCTLA MSR (to set up a circular BTSbuffer) or set the BTINT flag (to generate an interrupt when the BTS buffer isnearly full). For Intel Core Solo and Intel Core Duo processors, do the same inIA32_DEBUGCTL; in MSR_DEBUGCTLB for Pentium M processors.NOTESIf the buffer size is set to less than the minimum allowable value (i.e.BTS absolute maximum < 1 + size of BTS record), the results of BTSis undefined.In order to prevent generating an interrupt, when working withcircular BTS buffer, SW need to set BTS interrupt threshold to a valuegreater than BTS absolute maximum (fields of the DS buffermanagement area).
It's not enough to clear the BTINT flag itself only.18.6.8.4Setting Up CPL-Qualified BTSIf the processor supports CPL-qualified last branch recording mechanism, the generation of branch records and storing of them in the BTS buffer are determined by: TR,BTS, BTS_OFF_OS, BTS_OFF_USR, and BTINT. The encoding of these five bits areshown in Table 18-5.18-28 Vol. 3DEBUGGING AND PERFORMANCE MONITORINGTable 18-5. CPL-Qualified Branch Trace Store EncodingsTRBTSBTS_OFF_OSBTS_OFF_USRBTINTDescription0XXXXBranch trace messages (BTMs)off10XXXGenerates BTMs but do notstore BTMs11000Store all BTMs in the BTS buffer,used here as a circular buffer11100Store BTMs with CPL > 0 in theBTS buffer11010Store BTMs with CPL = 0 in theBTS buffer1111XGenerate BTMs but do not storeBTMs11001Store all BTMs in the BTS buffer;generate an interrupt when thebuffer is nearly full11101Store BTMs with CPL > 0 in theBTS buffer; generate aninterrupt when the buffer isnearly full11011Store BTMs with CPL = 0 in theBTS buffer; generate aninterrupt when the buffer isnearly full18.6.8.5Writing the DS Interrupt Service RoutineThe BTS, non-precise event-based sampling, and PEBS facilities share the sameinterrupt vector and interrupt service routine (called the debug store interruptservice routine or DS ISR).
To handle BTS, non-precise event-based sampling, andPEBS interrupts: separate handler routines must be included in the DS ISR. Use thefollowing guidelines when writing a DS ISR to handle BTS, non-precise event-basedsampling, and/or PEBS interrupts.•The DS interrupt service routine (ISR) must be part of a kernel driver and operateat a current privilege level of 0 to secure the buffer storage area.•Because the BTS, non-precise event-based sampling, and PEBS facilities sharethe same interrupt vector, the DS ISR must check for all the possible causes ofinterrupts from these facilities and pass control on to the appropriate handler.BTS and PEBS buffer overflow would be the sources of the interrupt if the bufferVol. 3 18-29DEBUGGING AND PERFORMANCE MONITORINGindex matches/exceeds the interrupt threshold specified. Detection of nonprecise event-based sampling as the source of the interrupt is accomplished bychecking for counter overflow.•There must be separate save areas, buffers, and state for each processor in anMP system.•Upon entering the ISR, branch trace messages and PEBS should be disabled toprevent race conditions during access to the DS save area.
This is done byclearing TR flag in the MSR_DEBUGCTLA MSR and by clearing the precise eventenable flag in the MSR_PEBS_ENABLE MSR. These settings should be restored totheir original values when exiting the ISR.•The processor will not disable the DS save area when the buffer is full and thecircular mode has not been selected. The current DS setting must be retainedand restored by the ISR on exit.•After reading the data in the appropriate buffer, up to but not including thecurrent index into the buffer, the ISR must reset the buffer index to the beginningof the buffer. Otherwise, everything up to the index will look like new entries uponthe next invocation of the ISR.••The ISR must clear the mask bit in the performance counter LVT entry.•The Pentium 4 Processor and Intel Xeon Processor mask PMIs upon receiving aninterrupt.
Clear this condition before leaving the interrupt handler.The ISR must re-enable the CCCR's ENABLE bit if it is servicing an overflow PMIdue to PEBS.18.7LAST BRANCH, INTERRUPT, AND EXCEPTIONRECORDING (INTEL® CORE™ SOLO AND INTEL®CORE™ DUO PROCESSORS)Intel Core Solo and Intel Core Duo processors provide last branch interrupt andexception recording. This capability is almost identical to that found in Pentium 4 andIntel Xeon processors. There are differences in the stack and in some MSR namesand locations.Note the following:•IA32_DEBUGCTL MSR — Enables debug trace interrupt, debug trace store,trace messages enable, performance monitoring breakpoint flags, singlestepping on branches, and last branch. IA32_DEBUGCTL MSR is located atregister address 01D9H.See Figure 18-7 the layout and the entries below for a description of the flags:— LBR (last branch/interrupt/exception) flag (bit 0) — When set, theprocessor records a running trace of the most recent branches, interrupts,and/or exceptions taken by the processor (prior to a debug exception being18-30 Vol.
3DEBUGGING AND PERFORMANCE MONITORINGgenerated) in the last branch record (LBR) stack. For more information, seethe “Last Branch Record (LBR) Stack” below.— BTF (single-step on branches) flag (bit 1) — When set, the processortreats the TF flag in the EFLAGS register as a “single-step on branches” flagrather than a “single-step on instructions” flag. This mechanism allowssingle-stepping the processor on taken branches, interrupts, and exceptions.See Section 18.6.5, “Single-Stepping on Branches, Exceptions, and Interrupts,” for more information about the BTF flag.— TR (trace message enable) flag (bit 6) — When set, branch tracemessages are enabled. When the processor detects a taken branch,interrupt, or exception; it sends the branch record out on the system bus asa branch trace message (BTM).
See Section 18.6.6, “Branch Trace Messages,”for more information about the TR flag.— BTS (branch trace store) flag (bit 7) — When set, the flag enables BTSfacilities to log BTMs to a memory-resident BTS buffer that is part of the DSsave area. See Section 18.15.5, “DS Save Area.”— BTINT (branch trace interrupt) flag (bits 8) — When set, the BTSfacilities generate an interrupt when the BTS buffer is full.
When clear, BTMs arelogged to the BTS buffer in a circular fashion. See Section 18.6.8, “Branch TraceStore (BTS),” for a description of this mechanism.318 7 6 5 4 3 2 1 0ReservedBTINT — Branch trace interruptBTS — Branch trace storeTR — Trace messages enableReservedBTF — Single-step on branchesLBR — Last branch/interrupt/exceptionFigure 18-7. IA32_DEBUGCTL MSR for Intel Core Soloand Intel Core Duo Processors•Debug store (DS) feature flag (bit 21), returned by the CPUIDinstruction — Indicates that the processor provides the debug store (DS)mechanism, which allows BTMs to be stored in a memory-resident BTS buffer.See Section 18.6.8, “Branch Trace Store (BTS).”•Last Branch Record (LBR) Stack — The LBR stack consists of 8 MSRs(MSR_LASTBRANCH_0 through MSR_LASTBRANCH_7); bits 31-0 hold the ‘from’address, bits 63-32 hold the ‘to’ address (MSR addresses start at 40H). SeeFigure 18-8.Vol.
3 18-31DEBUGGING AND PERFORMANCE MONITORING•Last Branch Record Top-of-Stack (TOS) Pointer — The TOS Pointer MSRcontains a 3-bit pointer (bits 2-0) to the MSR in the LBR stack that contains themost recent branch, interrupt, or exception recorded. For Intel Core Solo andIntel Core Duo processors, this MSR is located at register address 01C9H.For compatibility, the Intel Core Solo and Intel Core Duo processors provide two 32bit MSRs (the MSR_LER_TO_LIP and the MSR_LER_FROM_LIP MSRs) that duplicatefunctions of the LastExceptionToIP and LastExceptionFromIP MSRs found in P6 familyprocessors.For details, see Section 18.6, “Last Branch, Interrupt, and Exception Recording(Processors based on Intel NetBurst® Microarchitecture),” and Appendix B.3, “MSRsIn Intel® Core™ Solo and Intel® Core™ Duo Processors.”MSR_LASTBRANCH_0 through MSR_LASTBRANCH_763032 - 31To Linear AddressFrom Linear AddressFigure 18-8.
LBR Branch Record Layout for the Intel Core Soloand Intel Core Duo Processor18.8LAST BRANCH, INTERRUPT, AND EXCEPTIONRECORDING (PENTIUM M PROCESSORS)Like the Pentium 4 and Intel Xeon processor family, Pentium M processors providelast branch interrupt and exception recording. The capability operates almost identically to that found in Pentium 4 and Intel Xeon processors. There are differences inthe shape of the stack and in some MSR names and locations. Note the following:•MSR_DEBUGCTLB MSR — Enables debug trace interrupt, debug trace store,trace messages enable, performance monitoring breakpoint flags, singlestepping on branches, and last branch.
For Pentium M processors, this MSR islocated at register address 01D9H. See Figure 18-9 and the entries below for adescription of the flags.— LBR (last branch/interrupt/exception) flag (bit 0) — When set, theprocessor records a running trace of the most recent branches, interrupts,and/or exceptions taken by the processor (prior to a debug exception beinggenerated) in the last branch record (LBR) stack. For more information, seethe “Last Branch Record (LBR) Stack” bullet below.— BTF (single-step on branches) flag (bit 1) — When set, the processortreats the TF flag in the EFLAGS register as a “single-step on branches” flagrather than a “single-step on instructions” flag. This mechanism allows18-32 Vol. 3DEBUGGING AND PERFORMANCE MONITORINGsingle-stepping the processor on taken branches, interrupts, and exceptions.See Section 18.6.5, “Single-Stepping on Branches, Exceptions, and Interrupts,” for more information about the BTF flag.— PBi (performance monitoring/breakpoint pins) flags (bits 5-2) —When these flags are set, the performance monitoring/breakpoint pins on theprocessor (BP0#, BP1#, BP2#, and BP3#) report breakpoint matches in thecorresponding breakpoint-address registers (DR0 through DR3).
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
