Volume 3B System Programming Guide_ Part 2 (794104), страница 2
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When debug extensionsare not enabled (when the DE flag is clear), these registers are aliased to debugregisters DR6 and DR7.18.2.3Debug Status Register (DR6)The debug status register (DR6) reports debug conditions that were sampled at thetime the last debug exception was generated (see Figure 18-1). Updates to thisregister only occur when an exception is generated.
The flags in this register showthe following information:•B0 through B3 (breakpoint condition detected) flags (bits 0 through 3)— Indicates (when set) that its associated breakpoint condition was met when adebug exception was generated. These flags are set if the condition described foreach breakpoint by the LENn, and R/Wn flags in debug control register DR7 istrue. They are set even if the breakpoint is not enabled by the Ln and Gn flags inregister DR7.•BD (debug register access detected) flag (bit 13) — Indicates that the nextinstruction in the instruction stream accesses one of the debug registers (DR0through DR7). This flag is enabled when the GD (general detect) flag in debugcontrol register DR7 is set. See Section 18.2.4, “Debug Control Register (DR7),”for further explanation of the purpose of this flag.•BS (single step) flag (bit 14) — Indicates (when set) that the debug exceptionwas triggered by the single-step execution mode (enabled with the TF flag in theEFLAGS register).
The single-step mode is the highest-priority debug exception.When the BS flag is set, any of the other debug status bits also may be set.•BT (task switch) flag (bit 15) — Indicates (when set) that the debugexception resulted from a task switch where the T flag (debug trap flag) in theTSS of the target task was set.
See Section 6.2.1, “Task-State Segment (TSS),”for the format of a TSS. There is no flag in debug control register DR7 to enableor disable this exception; the T flag of the TSS is the only enabling flag.Certain debug exceptions may clear bits 0-3. The remaining contents of the DR6register are never cleared by the processor. To avoid confusion in identifying debug18-4 Vol. 3DEBUGGING AND PERFORMANCE MONITORINGexceptions, debug handlers should clear the register before returning to the interrupted task.18.2.4Debug Control Register (DR7)The debug control register (DR7) enables or disables breakpoints and sets breakpoint conditions (see Figure 18-1). The flags and fields in this register control thefollowing things:•L0 through L3 (local breakpoint enable) flags (bits 0, 2, 4, and 6) —Enables (when set) the breakpoint condition for the associated breakpoint for thecurrent task.
When a breakpoint condition is detected and its associated Ln flagis set, a debug exception is generated. The processor automatically clears theseflags on every task switch to avoid unwanted breakpoint conditions in the newtask.•G0 through G3 (global breakpoint enable) flags (bits 1, 3, 5, and 7) —Enables (when set) the breakpoint condition for the associated breakpoint for alltasks. When a breakpoint condition is detected and its associated Gn flag is set,a debug exception is generated. The processor does not clear these flags on atask switch, allowing a breakpoint to be enabled for all tasks.•LE and GE (local and global exact breakpoint enable) flags (bits 8, 9) —This feature is not supported in the P6 family processors, later IA-32 processors,and Intel 64 processors.
When set, these flags cause the processor to detect theexact instruction that caused a data breakpoint condition. For backward andforward compatibility with other Intel processors, we recommend that the LE andGE flags be set to 1 if exact breakpoints are required.•GD (general detect enable) flag (bit 13) — Enables (when set) debugregister protection, which causes a debug exception to be generated prior to anyMOV instruction that accesses a debug register. When such a condition isdetected, the BD flag in debug status register DR6 is set prior to generating theexception.
This condition is provided to support in-circuit emulators.When the emulator needs to access the debug registers, emulator software canset the GD flag to prevent interference from the program currently executing onthe processor.The processor clears the GD flag upon entering to the debug exception handler,to allow the handler access to the debug registers.•R/W0 through R/W3 (read/write) fields (bits 16, 17, 20, 21, 24, 25, 28,and 29) — Specifies the breakpoint condition for the corresponding breakpoint.The DE (debug extensions) flag in control register CR4 determines how the bits inthe R/Wn fields are interpreted.
When the DE flag is set, the processor interpretsbits as follows:00 — Break on instruction execution only.01 — Break on data writes only.Vol. 3 18-5DEBUGGING AND PERFORMANCE MONITORING10 — Break on I/O reads or writes.11 — Break on data reads or writes but not instruction fetches.When the DE flag is clear, the processor interprets the R/Wn bits the same as forthe Intel386™ and Intel486™ processors, which is as follows:00011011•————Break on instruction execution only.Break on data writes only.Undefined.Break on data reads or writes but not instruction fetches.LEN0 through LEN3 (Length) fields (bits 18, 19, 22, 23, 26, 27, 30, and31) — Specify the size of the memory location at the address specified in thecorresponding breakpoint address register (DR0 through DR3).
These fields areinterpreted as follows:00011011————1-byte length.2-byte length.Undefined (or 8 byte length, see note below).4-byte length.If the corresponding RWn field in register DR7 is 00 (instruction execution), then theLENn field should also be 00. The effect of using other lengths is undefined. SeeSection 18.2.5, “Breakpoint Field Recognition,” below.NOTESPentium®Intel®For4 andXeon® processors with a CPUID signaturecorresponding to family 15 (model 3, 4, and 6), break pointconditions permit specifying 8-byte length on data read/write with anof encoding 10B in the LENx field.Encoding 10B is also supported in processors based on Intel Coremicroarchitecture, with a CPUID signature corresponding to family 6,model 15. The encoding 10B is undefined for other processors.18.2.5Breakpoint Field RecognitionBreakpoint address registers (debug registers DR0 through DR3) and the LENn fieldsfor each breakpoint define a range of sequential byte addresses for a data or I/Obreakpoint.
The LENn fields permit specification of a 1-, 2-, 4-, or 8-byte range,beginning at the linear address specified in the corresponding debug register (DRn).Two-byte ranges must be aligned on word boundaries; 4-byte ranges must bealigned on doubleword boundaries. I/O breakpoint addresses are zero-extended(from 16 to 32 bits, for comparison with the breakpoint address in the selected debugregister). These requirements are enforced by the processor; it uses LENn field bitsto mask the lower address bits in the debug registers.
Unaligned data or I/O breakpoint addresses do not yield valid results.A data breakpoint for reading or writing data is triggered if any of the bytes participating in an access is within the range defined by a breakpoint address register and18-6 Vol. 3DEBUGGING AND PERFORMANCE MONITORINGits LENn field. Table 18-1 provides an example setup of debug registers and dataaccesses that would subsequently trap or not trap on the breakpoints.A data breakpoint for an unaligned operand can be constructed using two breakpoints, where each breakpoint is byte-aligned and the two breakpoints togethercover the operand.
The breakpoints generate exceptions only for the operand, not forneighboring bytes.Instruction breakpoint addresses must have a length specification of 1 byte (theLENn field is set to 00). Code breakpoints for other operand sizes are undefined. Theprocessor recognizes an instruction breakpoint address only when it points to thefirst byte of an instruction. If the instruction has prefixes, the breakpoint addressmust point to the first prefix.Table 18-1. Breakpoint ExamplesDebug Register SetupDebug RegisterR/WnBreakpoint AddressLENnDR0DR1DR2DR3R/W0 = 11 (Read/Write)R/W1 = 01 (Write)R/W2 = 11 (Read/Write)R/W3 = 01 (Write)A0001HA0002HB0002HC0000HLEN0 = 00 (1 byte)LEN1 = 00 (1 byte)LEN2 = 01) (2 bytes)LEN3 = 11 (4 bytes)Data AccessesOperationAddressAccess Length(In Bytes)Data operations that trap- Read or write- Read or write- Write- Write- Read or write- Read or write- Read or write- Write- Write- WriteA0001HA0001HA0002HA0002HB0001HB0002HB0002HC0000HC0001HC0003H1212412421Data operations that do not trap- Read or write- Read- Read or write- Read or write- Read- Read or writeA0000HA0002HA0003HB0000HC0000HC0004H114224Vol.
3 18-7DEBUGGING AND PERFORMANCE MONITORINGDebug Registers and Intel® 64 Processors18.2.6For Intel 64 architecture processors, debug registers DR0–DR7 are 64 bits. In 16-bitor 32-bit modes (protected mode and compatibility mode), writes to a debug registerfill the upper 32 bits with zeros. Reads from a debug register return the lower 32 bits.In 64-bit mode, MOV DRn instructions read or write all 64 bits. Operand-size prefixesare ignored.In 64-bit mode, the upper 32 bits of DR6 and DR7 are reserved and must be writtenwith zeros. Writing 1 to any of the upper 32 bits results in a #GP(0) exception (seeFigure 18-2). All 64 bits of DR0–DR3 are writable by software.
However, MOV DRninstructions do not check that addresses written to DR0–DR3 are in the linearaddress limits of the processor implementation (address matching is supported onlyon valid addresses generated by the processor implementation). Break point conditions for 8-byte memory read/writes are supported in all modes.6332DR731 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0LEN R/W LEN R/W LEN R/W LEN R/W 0 0 G 0 0 1 G L G L G L G L G LDR733221100DE E 3 3 2 2 1 1 0 06332DR63116 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0Reserved (set to 1)B B B 0 1 1 1 1 1 1 1 1 1 B B B BDR6T S D3 2 1 0ReservedFigure 18-2.
DR6/DR7 Layout on Processors Supporting Intel 64 Technology18.3DEBUG EXCEPTIONSThe Intel 64 and IA-32 architectures dedicate two interrupt vectors to handlingdebug exceptions: vector 1 (debug exception, #DB) and vector 3 (breakpoint exception, #BP). The following sections describe how these exceptions are generated andtypical exception handler operations.18-8 Vol. 3DEBUGGING AND PERFORMANCE MONITORING18.3.1Debug Exception (#DB)—Interrupt Vector 1The debug-exception handler is usually a debugger program or part of a larger software system.
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