Volume 3B System Programming Guide_ Part 2 (794104), страница 8
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Theprocessor asserts then deasserts the corresponding BPi# pin when abreakpoint match occurs. When a PBi flag is clear, the performancemonitoring/breakpoint pins report performance events. Processor executionis not affected by reporting performance events.— TR (trace message enable) flag (bit 6) — When set, branch tracemessages are enabled. When the processor detects a taken branch,interrupt, or exception, it sends the branch record out on the system bus as abranch trace message (BTM). See Section 18.6.6, “Branch Trace Messages,”for more information about the TR flag.— BTS (branch trace store) flag (bit 7) — When set, enables the BTSfacilities to log BTMs to a memory-resident BTS buffer that is part of the DSsave area. See Section 18.15.5, “DS Save Area.”— BTINT (branch trace interrupt) flag (bits 8) — When set, the BTSfacilities generate an interrupt when the BTS buffer is full.
When clear, BTMs arelogged to the BTS buffer in a circular fashion. See Section 18.6.8, “Branch TraceStore (BTS),” for a description of this mechanism.318 7 6 5 4 3 2 1 0ReservedBTINT — Branch trace interruptBTS — Branch trace storeTR — Trace messages enablePB3/2/1/0 — Performance monitoring breakpoint flagsBTF — Single-step on branchesLBR — Last branch/interrupt/exceptionFigure 18-9. MSR_DEBUGCTLB MSR for Pentium M Processors•Debug store (DS) feature flag (bit 21), returned by the CPUIDinstruction — Indicates that the processor provides the debug store (DS)mechanism, which allows BTMs to be stored in a memory-resident BTS buffer.See Section 18.6.8, “Branch Trace Store (BTS).”•Last Branch Record (LBR) Stack — The LBR stack consists of 8 MSRs(MSR_LASTBRANCH_0 through MSR_LASTBRANCH_7); bits 31-0 hold the ‘from’Vol.
3 18-33DEBUGGING AND PERFORMANCE MONITORINGaddress, bits 63-32 hold the ‘to’ address. For Pentium M Processors, these pairsare located at register addresses 040H-047H. See Figure 18-10.•Last Branch Record Top-of-Stack (TOS) Pointer — The TOS Pointer MSRcontains a 3-bit pointer (bits 2-0) to the MSR in the LBR stack that contains themost recent branch, interrupt, or exception recorded. For Pentium M Processors,this MSR is located at register address 01C9H.For compatibility, the Pentium M processor provides two 32-bit MSRs (theMSR_LER_TO_LIP and the MSR_LER_FROM_LIP MSRs) that duplicate the functionsof the LastExceptionToIP and LastExceptionFromIP MSRs found in P6 family processors.MSR_LASTBRANCH_063through MSR_LASTBRANCH_7032 - 31To Linear AddressFrom Linear AddressFigure 18-10.
LBR Branch Record Layout for the Pentium M ProcessorFor more detail on these capabilities, see Section 18.6, “Last Branch, Interrupt, andException Recording (Processors based on Intel NetBurst® Microarchitecture),” andAppendix B.4, “MSRs In the Pentium M Processor.”18.9LAST BRANCH, INTERRUPT, AND EXCEPTIONRECORDING (P6 FAMILY PROCESSORS)The P6 family processors provide five MSRs for recording the last branch, interrupt,or exception taken by the processor: DEBUGCTLMSR, LastBranchToIP, LastBranchFromIP, LastExceptionToIP, and LastExceptionFromIP.
These registers can be used tocollect last branch records, to set breakpoints on branches, interrupts, and exceptions, and to single-step from one branch to the next.See Appendix B, “Model-Specific Registers (MSRs),” for a detailed description of eachof the last branch recording MSRs.18.9.1DEBUGCTLMSR RegisterThe version of the DEBUGCTLMSR register found in the P6 family processors enableslast branch, interrupt, and exception recording; taken branch breakpoints; thebreakpoint reporting pins; and trace messages. This register can be written to usingthe WRMSR instruction, when operating at privilege level 0 or when in real-address18-34 Vol.
3DEBUGGING AND PERFORMANCE MONITORINGmode. A protected-mode operating system procedure is required to provide useraccess to this register. Figure 18-11 shows the flags in the DEBUGCTLMSR registerfor the P6 family processors. The functions of these flags are as follows:•LBR (last branch/interrupt/exception) flag (bit 0) — When set, theprocessor records the source and target addresses (in the LastBranchToIP,LastBranchFromIP, LastExceptionToIP, and LastExceptionFromIP MSRs) for thelast branch and the last exception or interrupt taken by the processor prior to adebug exception being generated. The processor clears this flag whenever adebug exception, such as an instruction or data breakpoint or single-step trapoccurs.317 6 5 4 3 2 1 0ReservedP P P P B LT B B B B T BR 3 2 1 0 F RTR — Trace messages enablePBi — Performance monitoring/breakpoint pinsBTF — Single-step on branchesLBR — Last branch/interrupt/exceptionFigure 18-11. DEBUGCTLMSR Register (P6 Family Processors)•BTF (single-step on branches) flag (bit 1) — When set, the processor treatsthe TF flag in the EFLAGS register as a “single-step on branches” flag.
SeeSection 18.6.5, “Single-Stepping on Branches, Exceptions, and Interrupts.”•PBi (performance monitoring/breakpoint pins) flags (bits 2 through 5)— When these flags are set, the performance monitoring/breakpoint pins on theprocessor (BP0#, BP1#, BP2#, and BP3#) report breakpoint matches in thecorresponding breakpoint-address registers (DR0 through DR3). The processorasserts then deasserts the corresponding BPi# pin when a breakpoint matchoccurs.
When a PBi flag is clear, the performance monitoring/breakpoint pinsreport performance events. Processor execution is not affected by reportingperformance events.•TR (trace message enable) flag (bit 6) — When set, trace messages areenabled as described in Section 18.6.6, “Branch Trace Messages.” Setting thisflag greatly reduces the performance of the processor. When trace messages areenabled, the values stored in the LastBranchToIP, LastBranchFromIP, LastExceptionToIP, and LastExceptionFromIP MSRs are undefined.Vol.
3 18-35DEBUGGING AND PERFORMANCE MONITORING18.9.2Last Branch and Last Exception MSRsThe LastBranchToIP and LastBranchFromIP MSRs are 32-bit registers for recordingthe instruction pointers for the last branch, interrupt, or exception that the processortook prior to a debug exception being generated. When a branch occurs, theprocessor loads the address of the branch instruction into the LastBranchFromIP MSRand loads the target address for the branch into the LastBranchToIP MSR.When an interrupt or exception occurs (other than a debug exception), the addressof the instruction that was interrupted by the exception or interrupt is loaded into theLastBranchFromIP MSR and the address of the exception or interrupt handler that iscalled is loaded into the LastBranchToIP MSR.The LastExceptionToIP and LastExceptionFromIP MSRs (also 32-bit registers) recordthe instruction pointers for the last branch that the processor took prior to an exception or interrupt being generated.
When an exception or interrupt occurs, thecontents of the LastBranchToIP and LastBranchFromIP MSRs are copied into theseregisters before the to and from addresses of the exception or interrupt are recordedin the LastBranchToIP and LastBranchFromIP MSRs.These registers can be read using the RDMSR instruction.Note that the values stored in the LastBranchToIP, LastBranchFromIP, LastExceptionToIP, and LastExceptionFromIP MSRs are offsets into the current code segment, asopposed to linear addresses, which are saved in last branch records for the Pentium4 and Intel Xeon processors.18.9.3Monitoring Branches, Exceptions, and InterruptsWhen the LBR flag in the DEBUGCTLMSR register is set, the processor automaticallybegins recording branches that it takes, exceptions that are generated (except fordebug exceptions), and interrupts that are serviced. Each time a branch, exception,or interrupt occurs, the processor records the to and from instruction pointers in theLastBranchToIP and LastBranchFromIP MSRs.
In addition, for interrupts and exceptions, the processor copies the contents of the LastBranchToIP and LastBranchFromIP MSRs into the LastExceptionToIP and LastExceptionFromIP MSRs prior torecording the to and from addresses of the interrupt or exception.When the processor generates a debug exception (#DB), it automatically clears theLBR flag before executing the exception handler, but does not touch the last branchand last exception MSRs. The addresses for the last branch, interrupt, or exceptiontaken are thus retained in the LastBranchToIP and LastBranchFromIP MSRs and theaddresses of the last branch prior to an interrupt or exception are retained in theLastExceptionToIP, and LastExceptionFromIP MSRs.The debugger can use the last branch, interrupt, and/or exception addresses incombination with code-segment selectors retrieved from the stack to reset breakpoints in the breakpoint-address registers (DR0 through DR3), allowing a backwardtrace from the manifestation of a particular bug toward its source.
Because theinstruction pointers recorded in the LastBranchToIP, LastBranchFromIP, LastExcepti-18-36 Vol. 3DEBUGGING AND PERFORMANCE MONITORINGonToIP, and LastExceptionFromIP MSRs are offsets into a code segment, softwaremust determine the segment base address of the code segment associated with thecontrol transfer to calculate the linear address to be placed in the breakpoint-addressregisters. The segment base address can be determined by reading the segmentselector for the code segment from the stack and using it to locate the segmentdescriptor for the segment in the GDT or LDT. The segment base address can then beread from the segment descriptor.Before resuming program execution from a debug-exception handler, the handlermust set the LBR flag again to re-enable last branch and last exception/interruptrecording.18.10TIME-STAMP COUNTERThe Intel 64 and IA-32 architectures (beginning with the Pentium processor) define atime-stamp counter mechanism that can be used to monitor and identify the relativetime occurrence of processor events.
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