Volume 3B System Programming Guide_ Part 2 (794104), страница 19
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3DEBUGGING AND PERFORMANCE MONITORINGCertain kinds of μops that cannot be tagged, including I/O, uncacheable and lockedaccesses, returns, and far transfers.Table A-6 lists the performance monitoring events that support at-retirementcounting: specifically the Front_end_event, Execution_event, Replay_event,Inst_retired and Uops_retired events. The following sections describe the taggingmechanisms for using these events to tag μop and count tagged μops.18.15.7.2 Tagging Mechanism for Front_end_eventThe Front_end_event counts μops that have been tagged as encountering any of thefollowing events:•μop decode events — Tagging μops for μop decode events requires specifyingbits in the ESCR associated with the performance-monitoring event, Uop_type.•Trace cache events — Tagging μops for trace cache events may requirespecifying certain bits in the MSR_TC_PRECISE_EVENT MSR (see Table A-8).Table A-6 describes the Front_end_event and Table A-8 describes metrics that areused to set up a Front_end_event count.The MSRs specified in the Table A-6 that are supported by the front-end taggingmechanism must be set and one or both of the NBOGUS and BOGUS bits in theFront_end_event event mask must be set to count events.
None of the eventscurrently supported requires the use of the MSR_TC_PRECISE_EVENT MSR.18.15.7.3 Tagging Mechanism For Execution_eventTable A-6 describes the Execution_event and Table A-9 describes metrics that areused to set up an Execution_event count.The execution tagging mechanism differs from other tagging mechanisms in how itcauses tagging. One upstream ESCR is used to specify an event to detect and tospecify a tag value (bits 5 through 8) to identify that event.
A second downstreamESCR is used to detect μops that have been tagged with that tag value identifier usingExecution_event for the event selection.The upstream ESCR that counts the event must have its tag enable flag (bit 4) setand must have an appropriate tag value mask entered in its tag value field. The 4-bittag value mask specifies which of tag bits should be set for a particular μop. Thevalue selected for the tag value should coincide with the event mask selected in thedownstream ESCR. For example, if a tag value of 1 is set, then the event mask ofNBOGUS0 should be enabled, correspondingly in the downstream ESCR.
The downstream ESCR detects and counts tagged μops. The normal (not tag value) mask bitsin the downstream ESCR specify which tag bits to count. If any one of the tag bitsselected by the mask is set, the related counter is incremented by one. This mechanism is summarized in the Table A-9 metrics that are supported by the executiontagging mechanism.
The tag enable and tag value bits are irrelevant for the downstream ESCR used to select the Execution_event.Vol. 3 18-87DEBUGGING AND PERFORMANCE MONITORINGThe four separate tag bits allow the user to simultaneously but distinctly count up tofour execution events at retirement. (This applies for non-precise event-basedsampling. There are additional restrictions for PEBS as noted in Section 18.15.8.3,“Setting Up the PEBS Buffer.”) It is also possible to detect or count combinations ofevents by setting multiple tag value bits in the upstream ESCR or multiple mask bitsin the downstream ESCR.
For example, use a tag value of 3H in the upstream ESCRand use NBOGUS0/NBOGUS1 in the downstream ESCR event mask.18.15.7.4 Tagging Mechanism for Replay_eventTable A-6 describes the Replay_event and Table A-10 describes metrics that are usedto set up an Replay_event count.The replay mechanism enables tagging of μops for a subset of all replays beforeretirement. Use of the replay mechanism requires selecting the type of μop that mayexperience the replay in the MSR_PEBS_MATRIX_VERT MSR and selecting the type ofevent in the MSR_PEBS_ENABLE MSR.
Replay tagging must also be enabled with theUOP_Tag flag (bit 24) in the MSR_PEBS_ENABLE MSR.The Table A-10 lists the metrics that are support the replay tagging mechanism andthe at-retirement events that use the replay tagging mechanism, and specifies howthe appropriate MSRs need to be configured. The replay tags defined in Table A-5also enable Precise Event-Based Sampling (PEBS, see Section 15.9.8). Each of thesereplay tags can also be used in normal sampling by not setting Bit 24 nor Bit 25 inIA_32_PEBS_ENABLE_MSR.
Each of these metrics requires that the Replay_Event(see Table A-6) be used to count the tagged μops.18.15.8 Precise Event-Based Sampling (PEBS)The debug store (DS) mechanism in processors based on Intel NetBurst microarchitecture allow two types of information to be collected for use in debugging and tuningprograms: PEBS records and BTS records. See Section 18.6.8, “Branch Trace Store(BTS),” for a description of the BTS mechanism.PEBS permits the saving of precise architectural information associated with one ormore performance events in the precise event records buffer, which is part of the DSsave area (see Section 18.15.5, “DS Save Area”).
To use this mechanism, a counteris configured to overflow after it has counted a preset number of events. After thecounter overflows, the processor copies the current state of the general-purpose andEFLAGS registers and instruction pointer into a record in the precise event recordsbuffer. The processor then resets the count in the performance counter and restartsthe counter. When the precise event records buffer is nearly full, an interrupt isgenerated, allowing the precise event records to be saved. A circular buffer is notsupported for precise event records.PEBS is supported only for a subset of the at-retirement events: Execution_event,Front_end_event, and Replay_event.
Also, PEBS can only be carried out using theone performance counter, the MSR_IQ_COUNTER4 MSR.18-88 Vol. 3DEBUGGING AND PERFORMANCE MONITORINGIn processors based on Intel Core microarchitecture, a similar PEBS mechanism isalso supported using IA32_PMC0 and IA32_PERFEVTSEL0 MSRs (See Section18.14.4).18.15.8.1 Detection of the Availability of the PEBS FacilitiesThe DS feature flag (bit 21) returned by the CPUID instruction indicates (when set)the availability of the DS mechanism in the processor, which supports the PEBS (andBTS) facilities. When this bit is set, the following PEBS facilities are available:•The PEBS_UNAVAILABLE flag in the IA32_MISC_ENABLE MSR indicates (whenclear) the availability of the PEBS facilities, including the MSR_PEBS_ENABLEMSR.•The enable PEBS flag (bit 24) in the MSR_PEBS_ENABLE MSR allows PEBS to beenabled (set) or disabled (clear).•The IA32_DS_AREA MSR can be programmed to point to the DS save area.18.15.8.2 Setting Up the DS Save AreaSection 18.6.8.2, “Setting Up the DS Save Area,” describes how to set up and enablethe DS save area.
This procedure is common for PEBS and BTS.18.15.8.3 Setting Up the PEBS BufferOnly the MSR_IQ_COUNTER4 performance counter can be used for PEBS. Use thefollowing procedure to set up the processor and this counter for PEBS:1. Set up the precise event buffering facilities. Place values in the precise eventbuffer base, precise event index, precise event absolute maximum, and preciseevent interrupt threshold, and precise event counter reset fields of the DS buffermanagement area (see Figure 18-24) to set up the precise event records bufferin memory.2.
Enable PEBS. Set the Enable PEBS flag (bit 24) in MSR_PEBS_ENABLE MSR.3. Set up the MSR_IQ_COUNTER4 performance counter and its associated CCCRand one or more ESCRs for PEBS as described in Tables A-6 through A-10.18.15.8.4 Writing a PEBS Interrupt Service RoutineThe PEBS facilities share the same interrupt vector and interrupt service routine(called the DS ISR) with the non-precise event-based sampling and BTS facilities. Tohandle PEBS interrupts, PEBS handler code must be included in the DS ISR. SeeSection 18.6.8.5, “Writing the DS Interrupt Service Routine,” for guidelines forwriting the DS ISR.Vol. 3 18-89DEBUGGING AND PERFORMANCE MONITORING18.15.8.5 Other DS Mechanism ImplicationsThe DS mechanism is not available in the SMM. It is disabled on transition to the SMMmode.
Similarly the DS mechanism is disabled on the generation of a machine checkexception and is cleared on processor RESET and INIT.The DS mechanism is available in real address mode.18.15.9 Operating System ImplicationsThe DS mechanism can be used by the operating system as a debugging extension tofacilitate failure analysis. When using this facility, a 25 to 30 times slowdown can beexpected due to the effects of the trace store occurring on every taken branch.Depending upon intended usage, the instruction pointers that are part of the branchrecords or the PEBS records need to have an association with the correspondingprocess.
One solution requires the ability for the DS specific operating systemmodule to be chained to the context switch. A separate buffer can then be maintained for each process of interest and the MSR pointing to the configuration areasaved and setup appropriately on each context switch.If the BTS facility has been enabled, then it must be disabled and state stored ontransition of the system to a sleep state in which processor context is lost. The statemust be restored on return from the sleep state.It is required that an interrupt gate be used for the DS interrupt as opposed to a trapgate to prevent the generation of an endless interrupt loop.Pages that contain buffers must have mappings to the same physical address for allprocesses/logical processors, such that any change to CR3 will not change DSaddresses.
If this requirement cannot be satisfied (that is, the feature is enabled ona per thread/process basis), then the operating system must ensure that the featureis enabled/disabled appropriately in the context switch code.18.16PERFORMANCE MONITORING AND HYPERTHREADING TECHNOLOGYThe performance monitoring capability of processors supporting Hyper-ThreadingTechnology is similar to that described in Section 18.15. However, the capability isextended so that:•Performance counters can be programmed to select events qualified by logicalprocessor IDs.•Performance monitoring interrupts can be directed to a specific logical processorwithin the physical processor.18-90 Vol. 3DEBUGGING AND PERFORMANCE MONITORINGThe sections below describe performance counters, event qualification by logicalprocessor ID, and special purpose bits in ESCRs/CCCRs.
They also describeMSR_PEBS_ENABLE, MSR_PEBS_MATRIX_VERT, and MSR_TC_PRECISE_EVENT.18.16.1 ESCR MSRsFigure 18-31 shows the layout of an ESCR MSR in processors supporting HyperThreading Technology.The functions of the flags and fields are as follows:•T1_USR flag, bit 0 — When set, events are counted when thread 1 (logicalprocessor 1) is executing at a current privilege level (CPL) of 1, 2, or 3.
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