Volume 3B System Programming Guide_ Part 2 (794104), страница 18
Текст из файла (страница 18)
This enables CASCNT4INTO0and OVF_PMI. An ISR can sample on instruction addresses in this case (do notset ENABLE, or CASCADE).4. Write the value FFFFF000H into counter 16.1.5. Write the value 0400060CH to MSR_CRU_ESCR2 (corresponding to selecting theNBOGNTAG and NBOGTAG event masks with qualification restricted to logicalprocessor 0).6. Write the value 00039000H to MSR_IQ_CCCR4 (set ENABLE bit, but notOVF_PMI).Another use for cascading is to locate stalled execution in a multithreaded application. Assume MOB replays in thread B cause thread A to stall.
Getting a sample of thestalled execution in this scenario could be accomplished by:1. Set up counter B to count MOB replays on thread B.2. Set up counter A to count resource stalls on thread A; set its force overflow bitand the appropriate CASCNTxINTOy bit.3. Use the performance monitoring interrupt to capture the program execution dataof the stalled thread.Vol. 3 18-83DEBUGGING AND PERFORMANCE MONITORING18.15.6.8 Generating an Interrupt on OverflowAny performance counter can be configured to generate a performance monitorinterrupt (PMI) if the counter overflows.
The PMI interrupt service routine can thencollect information about the state of the processor or program when overflowoccurred. This information can then be used with a tool like the Intel® VTune™Performance Analyzer to analyze and tune program performance.To enable an interrupt on counter overflow, the OVR_PMI flag in the counter’s associated CCCR MSR must be set. When overflow occurs, a PMI is generated through thelocal APIC. (Here, the performance counter entry in the local vector table [LVT] is setup to deliver the interrupt generated by the PMI to the processor.)The PMI service routine can use the OVF flag to determine which counter overflowedwhen multiple counters have been configured to generate PMIs.
Also, note that theseprocessors mask PMIs upon receiving an interrupt. Clear this condition before leavingthe interrupt handler.When generating interrupts on overflow, the performance counter being used shouldbe preset to value that will cause an overflow after a specified number of events arecounted plus 1. The simplest way to select the preset value is to write a negativenumber into the counter, as described in Section 18.15.6.6, “Cascading Counters.”Here, however, if an interrupt is to be generated after 100 event counts, the countershould be preset to minus 100 plus 1 (-100 + 1), or -99. The counter will then overflow after it counts 99 events and generate an interrupt on the next (100th) eventcounted.
The difference of 1 for this count enables the interrupt to be generatedimmediately after the selected event count has been reached, instead of waiting forthe overflow to be propagation through the counter.Because of latency in the microarchitecture between the generation of events andthe generation of interrupts on overflow, it is sometimes difficult to generate aninterrupt close to an event that caused it.
In these situations, the FORCE_OVF flag inthe CCCR can be used to improve reporting. Setting this flag causes the counter tooverflow on every counter increment, which in turn triggers an interrupt after everycounter increment.18.15.6.9 Counter Usage GuidelineThere are some instances where the user must take care to configure counting logicproperly, so that it is not powered down. To use any ESCR, even when it is being usedjust for tagging, (any) one of the counters that the particular ESCR (or its pairedESCR) can be connected to should be enabled.
If this is not done, 0 counts mayresult. Likewise, to use any counter, there must be some event selected in a corresponding ESCR (other than no_event, which generally has a select value of 0).18-84 Vol. 3DEBUGGING AND PERFORMANCE MONITORING18.15.7 At-Retirement CountingAt-retirement counting provides a means counting only events that represent workcommitted to architectural state and ignoring work that was performed speculativelyand later discarded.The Intel NetBurst microarchitecture used in the Pentium 4 and Intel Xeon processors performs many speculative activities in an attempt to increase effectiveprocessing speeds.
One example of this speculative activity is branch prediction. ThePentium 4 and Intel Xeon processors typically predict the direction of branches andthen decode and execute instructions down the predicted path in anticipation of theactual branch decision. When a branch misprediction occurs, the results of instructions that were decoded and executed down the mispredicted path are canceled. If aperformance counter was set up to count all executed instructions, the count wouldinclude instructions whose results were canceled as well as those whose resultscommitted to architectural state.To provide finer granularity in event counting in these situations, the performancemonitoring facilities provided in the Pentium 4 and Intel Xeon processors provide amechanism for tagging events and then counting only those tagged events thatrepresent committed results.
This mechanism is called “at-retirement counting.”Tables A-6 through A-10 list predefined at-retirement events and event metrics thatcan be used to for tagging events when using at retirement counting. The followingterminology is used in describing at-retirement counting:•Bogus, non-bogus, retire — In at-retirement event descriptions, the term“bogus” refers to instructions or μops that must be canceled because they are ona path taken from a mispredicted branch. The terms “retired” and “non-bogus”refer to instructions or μops along the path that results in committed architectural state changes as required by the program being executed.
Thus instructionsand μops are either bogus or non-bogus, but not both. Several of the Pentium 4and Intel Xeon processors’ performance monitoring events (such as,Instruction_Retired and Uops_Retired in Table A-6) can count instructions orμops that are retired based on the characterization of bogus” versus non-bogus.•Tagging — Tagging is a means of marking μops that have encountered aparticular performance event so they can be counted at retirement. During thecourse of execution, the same event can happen more than once per μop and adirect count of the event would not provide an indication of how many μopsencountered that event.The tagging mechanisms allow a μop to be tagged once during its lifetime andthus counted once at retirement.
The retired suffix is used for performancemetrics that increment a count once per μop, rather than once per event. Forexample, a μop may encounter a cache miss more than once during its life time,but a “Miss Retired” metric (that counts the number of retired μops thatencountered a cache miss) will increment only once for that μop. A “Miss Retired”metric would be useful for characterizing the performance of the cache hierarchyfor a particular instruction sequence. Details of various performance metrics andhow these can be constructed using the Pentium 4 and Intel Xeon processorsVol.
3 18-85DEBUGGING AND PERFORMANCE MONITORINGperformance events are provided in the Intel Pentium 4 Processor OptimizationReference Manual (see Section 1.4, “Related Literature”).•Replay — To maximize performance for the common case, the Intel NetBurstmicroarchitecture aggressively schedules μops for execution before all theconditions for correct execution are guaranteed to be satisfied.
In the event thatall of these conditions are not satisfied, μops must be reissued. The mechanismthat the Pentium 4 and Intel Xeon processors use for this reissuing of μops iscalled replay. Some examples of replay causes are cache misses, dependenceviolations, and unforeseen resource constraints. In normal operation, somenumber of replays is common and unavoidable.
An excessive number of replaysis an indication of a performance problem.•Assist — When the hardware needs the assistance of microcode to deal withsome event, the machine takes an assist. One example of this is an underflowcondition in the input operands of a floating-point operation. The hardware mustinternally modify the format of the operands in order to perform the computation.Assists clear the entire machine of μops before they begin and are costly.18.15.7.1 Using At-Retirement CountingThe Pentium 4 and Intel Xeon processors allow counting both events and μops thatencountered a specified event.
For a subset of the at-retirement events listed in TableA-6, a μop may be tagged when it encounters that event. The tagging mechanismscan be used in non-precise event-based sampling, and a subset of these mechanismscan be used in PEBS. There are four independent tagging mechanisms, and eachmechanism uses a different event to count μops tagged with that mechanism:•Front-end tagging — This mechanism pertains to the tagging of μops thatencountered front-end events (for example, trace cache and instruction counts)and are counted with the Front_end_event event•Execution tagging — This mechanism pertains to the tagging of μops thatencountered execution events (for example, instruction types) and are countedwith the Execution_Event event.•Replay tagging — This mechanism pertains to tagging of μops whoseretirement is replayed (for example, a cache miss) and are counted with theReplay_event event. Branch mispredictions are also tagged with this mechanism.•No tags — This mechanism does not use tags.
It uses the Instr_retired and theUops_ retired events.Each tagging mechanism is independent from all others; that is, a μop that has beentagged using one mechanism will not be detected with another mechanism’s taggedμop detector. For example, if μops are tagged using the front-end tagging mechanisms, the Replay_event will not count those as tagged μops unless they are alsotagged using the replay tagging mechanism. However, execution tags allow up tofour different types of μops to be counted at retirement through execution tagging.The independence of tagging mechanisms does not hold when using PEBS. Whenusing PEBS, only one tagging mechanism should be used at a time.18-86 Vol.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
