Volume 3B System Programming Guide_ Part 2 (794104), страница 34
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That is, a linear access does notcause an APIC-access VM exit if it would cause a page fault.•A linear access does not cause an APIC-access VM exit until after the accessedbits are set in the paging structures.•A linear write access will not cause an APIC-access VM exit until after the dirty bitis set in the appropriate paging structure.•With respect to all other events, any APIC-access VM exit due to a linear accesshas the same priority as any page fault that the linear access could cause.
(Thisitem applies to other events that the linear access may generate as well as eventsthat may be generated by other accesses by the same instruction or operation.)These principles imply among other things, that an APIC-access VM exit may occurduring the execution of a repeated string instruction (including INS and OUTS).Suppose, for example, that the first n iterations (n may be 0) of such an instructiondo not access the APIC-access page and that the next iteration does access thatpage.
As a result, the first n iterations may complete and be followed by an APICaccess VM exit. The instruction pointer saved in the VMCS references the repeatedstring instruction and the values of the general-purpose registers reflect the completion of n iterations.21-6 Vol. 3VMX NON-ROOT OPERATION21.2.1.3Instructions That May Cause Page Faults Without AccessingMemoryAPIC-access VM exits may occur as a result of executing an instruction that cancause a page fault even if that instruction would not access the APIC-access page.The following are some examples:•The CLFLUSH instruction is considered to read from the linear address in itssource operand. If that address translates to one on the APIC-access page, theinstruction causes an APIC-access VM exit.•The ENTER instruction causes a page fault if the byte referenced by the finalvalue of the stack pointer is not writable (even though ENTER does not write tothat byte if its size operand is non-zero).
If that byte is writable but is on theAPIC-access page, ENTER causes an APIC-access VM exit.1•An execution of the MASKMOVQ or MASKMOVDQU instructions with a zero maskmay or may not cause a page fault if the destination page is unwritable (thebehavior is implementation-specific). An execution with a zero mask causes anAPIC-access VM exit only on processors for which it could cause a page fault.•The MONITOR instruction is considered to read from the effective address in EAX.If the linear address corresponding to that address translates to one on the APICaccess page, the instruction causes an APIC-access VM exit.•An execution of the PREFETCH instruction that would result in an access to theAPIC-access page does not cause an APIC-access VM exit.21.2.2Physical Accesses to the APIC-Access PageAn access to the APIC-access page is called a physical access if (1) it is not generated by a linear address; or (2) its physical address is not the translation of theaccess’s linear address.
Physical accesses include the following:••••Reads from the page tables when translating a linear address.Loads of the page-directory pointers by MOV CR when CR4.PAE = 1.Updates to the accessed and dirty bits in the page tables.Any of the following accesses made by the processor to support VMX non-rootoperation:— Accesses to the VMCS region.— Accesses to data structures referenced (directly or indirectly) by physicaladdresses in VM-execution control fields in the VMCS.
These include the I/Obitmaps, the MSR bitmaps, and the virtual-APIC page.1. The ENTER instruction may also cause page faults due to the memory accesses that it actuallydoes perform. With regard to APIC-access VM exits, these are treated just as accesses by anyother instruction.Vol. 3 21-7VMX NON-ROOT OPERATION•Accesses that effect transitions into and out of SMM.1 These include thefollowing:— Accesses to SMRAM during SMI delivery and during execution of RSM.— Accesses during SMM VM exits (including accesses to MSEG) and duringVM entries that return from SMM.A physical access to the APIC-access page may or may not cause an APIC-accessVM exit. The priority of an APIC-access VM exit caused by physical access is notdefined relative to other events that the access may cause. Section 21.5.2 describesthe treatment of physical accesses to the APIC-access page that do not cause APICaccess VM exits.It is recommended that software not set the APIC-access address to any of thoseused by physical memory accesses (identified above).
For example, it should not setthe APIC-access address to the physical address of any of the active paging structures.21.2.3VTPR AccessesA memory access is a VTPR access if all of the following hold: (1) the “use TPRshadow” VM-execution control is 1; (2) the access is not for an instruction fetch;(3) the access is at most 32 bits in width; and (4) the access is to offset 80H on theAPIC-access page.A memory access is not a VTPR access (even if it accesses only bytes in the range80H–83H on the APIC-access page) if any of the following hold: (1) the “use TPRshadow” VM-execution control is 0; (2) the access is for an instruction fetch; (3) theaccess is more than 32 bits in width; or (4) the access is to some offset is on theAPIC-access page other than 80H.
For example, a 16-bit access to offset 81H on theAPIC-access page is not a VTPR access, even if the “use TPR shadow” VM-executioncontrol is 1.In general, VTPR accesses do not cause APIC-access VM exits. Instead, they aretreated as described in Section 21.5.3. Physical VTPR accesses (see Section 21.2.2)may or may not cause APIC-access VM exits; see Section 21.5.2.21.3OTHER CAUSES OF VM EXITSIn addition to VM exits caused by instruction execution, the following events cancause VM exits:•Exceptions.
Exceptions (faults, traps, and aborts) cause VM exits based on theexception bitmap (see Section 20.6.3). If an exception occurs, its vector (in the1. Technically, these accesses do not occur in VMX non-root operation. They are included here forclarity.21-8 Vol.
3VMX NON-ROOT OPERATIONrange 0–31) is used to select a bit in the exception bitmap. If the bit is 1, aVM exit occurs; if the bit is 0, the exception is delivered normally through theguest IDT. This use of the exception bitmap applies also to exceptions generatedby the instructions INT3, INTO, BOUND, and UD2.Page faults (exceptions with vector 14) are specially treated. When a page faultoccurs, a logical processor consults (1) bit 14 of the exception bitmap; (2) theerror code produced with the page fault [PFEC]; (3) the page-fault error-codemask field [PFEC_MASK]; and (4) the page-fault error-code match field[PFEC_MATCH].
It checks if PFEC & PFEC_MASK = PFEC_MATCH. If there isequality, the specification of bit 14 in the exception bitmap is followed (forexample, a VM exit occurs if that bit is set). If there is inequality, the meaning ofthat bit is reversed (for example, a VM exit occurs if that bit is clear).Thus, if the design requires VM exits on all page faults, software can set bit 14 inthe exception bitmap to 1 and set the page-fault error-code mask and matchfields each to 00000000H. If the design does not require VM exits on page faults,software could set bit 14 in the exception bitmap to 1, set the page-fault errorcode mask field to 00000000H, and set the page-fault error-code match field toFFFFFFFFH.•External interrupts.
An external interrupt causes a VM exit if the “externalinterrupt exiting” VM-execution control is 1. Otherwise, the interrupt is deliverednormally through the IDT. (If a logical processor is in the shutdown state or thewait-for-SIPI state, external interrupts are blocked. The interrupt is not deliveredthrough the IDT and no VM exit occurs.)•Non-maskable interrupts (NMIs). An NMI causes a VM exit if the “NMIexiting” VM-execution control is 1. Otherwise, it is delivered using descriptor 2 ofthe IDT.
(If a logical processor is in the wait-for-SIPI state, NMIs are blocked. TheNMI is not delivered through the IDT and no VM exit occurs.)•INIT signals. INIT signals cause VM exits. A logical processor performs none ofthe operations normally associated with these events. Such exits do not modifyregister state or clear pending events as they would outside of VMX operation. (Ifa logical processor is in the wait-for-SIPI state, INIT signals are blocked.
They donot cause VM exits in this case.)•Start-up IPIs (SIPIs). SIPIs cause VM exits. If a logical processor is not inthe wait-for-SIPI activity state when a SIPI arrives, no VM exit occurs and theSIPI is discarded. VM exits due to SIPIs do not perform any of the normaloperations associated with those events: they do not modify register state asthey would outside of VMX operation. (If a logical processor is not in the wait-forSIPI state, SIPIs are blocked. They do not cause VM exits in this case.)•Task switches.
Task switches are not allowed in VMX non-root operation. Anyattempt to effect a task switch in VMX non-root operation causes a VM exit. SeeSection 21.6.2.•System-management interrupts (SMIs). If the logical processor is using thedual-monitor treatment of SMIs and system-management mode (SMM), SMIscause SMM VM exits. See Section 24.16.2.1Vol. 3 21-9VMX NON-ROOT OPERATIONIn addition, there are controls that cause VM exits based on the readiness of guestsoftware to receive interrupts:•If the “interrupt-window exiting” VM-execution control is 1, a VM exit occursbefore execution of any instruction if RFLAGS.IF = 11 and there is no blocking ofevents by STI or by MOV SS (see Table 20-3). Such a VM exit occurs immediatelyafter VM entry if the above conditions are true (see Section 22.6.4).Non-maskable interrupts (NMIs) and higher priority events take priority overVM exits caused by this control.
VM exits caused by this control take priority overexternal interrupts and lower priority events.These VM exits wake a logical processor from the same inactive states as wouldan external interrupt. Specifically, they wake a logical processor from the statesentered using the HLT and MWAIT instructions. These VM exits do not occur if thelogical processor is in the shutdown state or the wait-for-SIPI state.•If the “NMI-window exiting” VM-execution control is 1, a VM exit occurs beforeexecution of any instruction if there is no virtual-NMI blocking and there is noblocking of events by MOV SS (see Table 20-3).
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