Volume 3B System Programming Guide_ Part 2 (794104), страница 51
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The VMX-abort indicatorallows software on one logical processor to diagnose the VMX-abort on another. For1. Note the following about processors that support Intel 64 architecture. If CR0.PG = 1, WRMSR tothe IA32_EFER MSR causes a general-protection exception if it would modify the LME bit. SinceCR0.PG is always 1 in VMX operation, the IA32_EFER MSR should not be included in the VM-exitMSR-load area for the purpose of modifying the LME bit.Vol. 3 23-29VM EXITSthis reason, it is recommended that software running in VMX root operation zero theVMX-abort indicator in the VMCS region of any VMCS that it uses.After saving the VMX-abort indicator, the logical processor experiencing a VMX abortissues a special bus cycle (to notify the chipset) and enters the VMX-abort shutdown state.
RESET is the only event that wakes a logical processor from the VMXabort shutdown state. The following events do not affect a logical processor in thisstate: machine checks; INIT signals; external interrupts; non-maskable interrupts(NMIs); start-up IPIs (SIPIs); and system-management interrupts (SMIs).23.8MACHINE CHECK DURING VM EXITIf a machine check occurs during VM exit, one of the following occurs:•The machine check is handled normally. If CR4.MCE = 1, a machine-checkexception (#MC) delivered through the guest IDT.
If CR4.MCE = 0, the processorgoes to the shutdown state.•A VMX abort is generated (see Section 23.7). The logical processor blocks eventsas done normally in VMX abort. The VMX abort indicator is 5, for “machine checkduring VM exit.”The first option is not used if the machine check occurs after any host state has beenloaded.23-30 Vol. 3CHAPTER 24SYSTEM MANAGEMENTThis chapter describes aspects of IA-64 and IA-32 architecture used in systemmanagement mode (SMM).SMM provides an alternate operating environment that can be used to monitor andmanage various system resources for more efficient energy usage, to control systemhardware, and/or to run proprietary code.
It was introduced into the IA-32 architecture in the Intel386 SL processor (a mobile specialized version of the Intel386processor). It is also available in the Pentium M, Pentium 4, Intel Xeon, P6 family, andPentium and Intel486 processors (beginning with the enhanced versions of theIntel486 SL and Intel486 processors).24.1SYSTEM MANAGEMENT MODE OVERVIEWSMM is a special-purpose operating mode provided for handling system-wide functions like power management, system hardware control, or proprietary OEMdesigned code. It is intended for use only by system firmware, not by applicationssoftware or general-purpose systems software.
The main benefit of SMM is that itoffers a distinct and easily isolated processor environment that operates transparently to the operating system or executive and software applications.When SMM is invoked through a system management interrupt (SMI), the processorsaves the current state of the processor (the processor’s context), then switches to aseparate operating environment contained in system management RAM (SMRAM).While in SMM, the processor executes SMI handler code to perform operations suchas powering down unused disk drives or monitors, executing proprietary code, orplacing the whole system in a suspended state.
When the SMI handler has completedits operations, it executes a resume (RSM) instruction. This instruction causes theprocessor to reload the saved context of the processor, switch back to protected orreal mode, and resume executing the interrupted application or operating-systemprogram or task.The following SMM mechanisms make it transparent to applications programs andoperating systems:••The only way to enter SMM is by means of an SMI.•Upon entering SMM, the processor saves the context of the interrupted programor task.The processor executes SMM code in a separate address space (SMRAM) that canbe made inaccessible from the other operating modes.Vol.
3 24-1SYSTEM MANAGEMENT•All interrupts normally handled by the operating system are disabled upon entryinto SMM.•The RSM instruction can be executed only in SMM.SMM is similar to real-address mode in that there are no privilege levels or addressmapping. An SMM program can address up to 4 GBytes of memory and can executeall I/O and applicable system instructions. See Section 24.5 for more informationabout the SMM execution environment.NOTESThe physical address extension (PAE) mechanism introduced in theP6 family processors is not supported when a processor is in SMM.The IA-32e mode address-translation mechanism is not supported inSMM.
See Section 3.10 of Intel® 64 and IA-32 ArchitecturesSoftware Developer’s Manual, Volume 3A.24.1.1System Management Mode and VMX OperationTraditionally, SMM services system management interrupts and then resumesprogram execution (back to the software stack consisting of executive and application software; see Section 24.2 through Section 24.14).A virtual machine monitor (VMM) using VMX can act as a host to multiple virtualmachines and each virtual machine can support its own software stack of executiveand application software. On processors that support VMX, virtual-machine extensions may use system-management interrupts (SMIs) and system-managementmode (SMM) in one of two ways:•Default treatment.
System firmware handles SMIs. The processor saves architectural states and critical states relevant to VMX operation upon entering SMM.When the firmware completes servicing SMIs, it uses RSM to resume VMXoperation.•Dual-monitor treatment. Two VM monitors collaborate to control the servicingof SMIs: one VMM operates outside of SMM to provide basic virtualization insupport for guests; the other VMM operates inside SMM (while in VMX operation)to support system-management functions.
The former is referred to asexecutive monitor, the latter SMM monitor.1The default treatment is described in Section 24.15, “Default Treatment of SMIs andSMM with VMX”. Dual-monitor treatment of SMM is described in Section 24.16,“Dual-Monitor Treatment of SMIs and SMM”.1. The dual-monitor treatment may not be supported by all processors.
Software should consult theVMX capability MSR IA32_VMX_BASIC (see Appendix G.1) to determine whether it is supported.24-2 Vol. 3SYSTEM MANAGEMENT24.2SYSTEM MANAGEMENT INTERRUPT (SMI)The only way to enter SMM is by signaling an SMI through the SMI# pin on theprocessor or through an SMI message received through the APIC bus. The SMI is anonmaskable external interrupt that operates independently from the processor’sinterrupt- and exception-handling mechanism and the local APIC. The SMI takesprecedence over an NMI and a maskable interrupt.
SMM is non-reentrant; that is, theSMI is disabled while the processor is in SMM.NOTESIn the Pentium 4, Intel Xeon, and P6 family processors, when aprocessor that is designated as an application processor during an MPinitialization sequence is waiting for a startup IPI (SIPI), it is in amode where SMIs are masked. However if a SMI is received while anapplication processor is in the wait for SIPI mode, the SMI will bepended.
The processor then responds on receipt of a SIPI byimmediately servicing the pended SMI and going into SMM beforehandling the SIPI.An SMI may be blocked for one macroinstruction following an STI,MOVSS or POPSS.24.3SWITCHING BETWEEN SMM AND THE OTHERPROCESSOR OPERATING MODESFigure 2-3 shows how the processor moves between SMM and the other processoroperating modes (protected, real-address, and virtual-8086). Signaling an SMI whilethe processor is in real-address, protected, or virtual-8086 modes always causes theprocessor to switch to SMM. Upon execution of the RSM instruction, the processoralways returns to the mode it was in when the SMI occurred.24.3.1Entering SMMThe processor always handles an SMI on an architecturally defined “interruptible”point in program execution (which is commonly at an IA-32 architecture instructionboundary).
When the processor receives an SMI, it waits for all instructions to retireand for all stores to complete. The processor then saves its current context in SMRAM(see Section 24.4), enters SMM, and begins to execute the SMI handler.Upon entering SMM, the processor signals external hardware that SMM handling hasbegun. The signaling mechanism used is implementation dependent. For the P6family processors, an SMI acknowledge transaction is generated on the system busand the multiplexed status signal EXF4 is asserted each time a bus transaction isgenerated while the processor is in SMM.
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