Volume 3B System Programming Guide_ Part 2 (794104), страница 46
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If the instruction has no displacement (forexample, has a register operand), zero is stored into the exit qualification.On processors that support Intel 64 architecture, an exception is made forRIP-relative addressing (used only in 64-bit mode). Such addressing causesan instruction to use an address that is the sum of the displacement fieldand the value of RIP that references the following instruction. In this case,the exit qualification is loaded with the sum of the displacement field andthe appropriate RIP value.In all cases, bits of this field beyond the instruction’s address size areundefined.
For example, suppose that the address-size field in the VM-exitinstruction-information field (see Section 20.9.4 and Section 23.2.4) reportsan n-bit address size. Then bits 63:n (bits 31:n on processors that do notsupport Intel 64 architecture) of the instruction displacement are undefined.— For control-register accesses, the exit qualification contains informationabout the access and has the format given in Table 23-3.Table 23-3. Exit Qualification for Control-Register AccessesBit PositionsContents3:0Number of control register (0 for CLTS and LMSW). Bit 3 is always 0 onprocessors that do not support Intel 64 architecture as they do not support CR8.5:4Access type:0 = MOV to CR1 = MOV from CR2 = CLTS3 = LMSW6LMSW operand type:0 = register1 = memoryFor CLTS and MOV CR, cleared to 07Reserved (cleared to 0)Vol.
3 23-7VM EXITSTable 23-3. Exit Qualification for Control-Register Accesses (Contd.)Bit PositionsContents11:8For MOV CR, the general-purpose register:0 = RAX1 = RCX2 = RDX3 = RBX4 = RSP5 = RBP6 = RSI7 = RDI8–15 represent R8–R15, respectively (used only on processors that supportIntel 64 architecture)For CLTS and LMSW, cleared to 015:1231:16Reserved (cleared to 0)For LMSW, the LMSW source dataFor CLTS and MOV CR, cleared to 063:32Reserved (cleared to 0). These bits exist only on processors that support Intel64 architecture.— For MOV DR, the exit qualification contains information about the instructionand has the format given in Table 23-4.Table 23-4. Exit Qualification for MOV DRBit Position(s)Contents2:0Number of debug register3Reserved (cleared to 0)4Direction of access (0 = MOV to DR; 17:5Reserved (cleared to 0)23-8 Vol.
3= MOV from DR)VM EXITSTable 23-4. Exit Qualification for MOV DR (Contd.)Bit Position(s)Contents11:8General-purpose register:0 = RAX1 = RCX2 = RDX3 = RBX4 = RSP5 = RBP6 = RSI7 = RDI8 –15 = R8 – R15, respectively63:12Reserved (cleared to 0)— For I/O instructions, the exit qualification contains information about theinstruction and has the format given in Table 23-5.Table 23-5. Exit Qualification for I/O InstructionsBit Position(s)Contents2:0Size of access:0 = 1-byte1 = 2-byte3 = 4-byteOther values not used3Direction of the attempted access (04String instruction (0 = not string; 1 = string)5REP prefixed (0 = not REP; 1 = REP)6Operand encoding (0 = DX, 1 = immediate)15:7Reserved (cleared to 0)31:16Port number (as specified in the I/O instruction)63:32Reserved (cleared to 0). These bits exist only on processors that support Intel64 architecture.= OUT, 1 = IN)Vol.
3 23-9VM EXITS— MWAIT. A value that indicates whether address-range monitoring hardwarewas armed. The exit qualification is set to either 0 (if address-rangemonitoring hardware is not armed) or 1 (if address-range monitoringhardware is armed).— For APIC-access VM exits resulting from linear accesses to the APIC-accesspage (see Section 21.2.1), the exit qualification contains information aboutthe instruction and has the format given in Table 23-6.1Table 23-6. Exit Qualification for APIC-Access VM Exits from Linear AccessesBit Position(s)Contents11:0Offset of access within the APIC page13:12Access type:0 = data read during instruction execution1 = data write during instruction execution2 = instruction fetch3 = access (read or write) during event delivery63:14Reserved (cleared to 0). Bits 63:32 exist only on processors that supportIntel 64 architecture.Such VM exits that set bits 13:12 of the exit qualification to 00b (data readduring instruction execution) or 01b (data write during instruction execution)set bit 12—which distinguishes data read from data write—to that whichwould have been stored in bit 1—W/R—of the page-fault error code had theaccess caused a page fault instead of an APIC-access VM exit.
This impliesthe following:•For APIC-access VM exits caused by the CLFLUSH instruction, the accesstype is “data read during instruction execution.”•For APIC-access VM exits caused by the ENTER instruction, the accesstype is “data write during instruction execution.”•For APIC-access VM exits caused by the MASKMOVQ and MASKMOVDQUinstructions, the access type is “data write during instruction execution.”•For APIC-access VM exits caused by the MONITOR instruction, the accesstype is “data read during instruction execution.”See Section 21.2.1.3 for further discussion of these instructions and APICaccess VM exits.1. The exit qualification is undefined if the access was part of the logging of a branch record or aprecise-event-based-sampling (PEBS) record to the DS save area. It is recommended that software configure the paging structures so that no address in the DS save area translates to anaddress on the APIC-access page.23-10 Vol.
3VM EXITSFor APIC-access VM exits resulting from physical accesses, the APIC-accesspage (see Section 21.2.2), the exit qualification is undefined.23.2.2Information for VM Exits Due to Vectored EventsSection 20.9.2 defines fields containing information for VM exits due to the followingevents: exceptions (including those generated by the instructions INT3, INTO,BOUND, and UD2); external interrupts that occur while the “acknowledge interrupton exit” VM-exit control is 1; and non-maskable interrupts (NMIs).
Such VM exitsinclude those that occur on an attempt at a task switch that causes an exceptionbefore generating the VM exit due to the task switch that causes the VM exit.The following items detail the use of these fields:•VM-exit interruption information (format given in Table 20-13). The followingitems detail how this field is established for VM exits due to these events:— For an exception, bits 7:0 receive the exception vector (at most 31). For anNMI, bits 7:0 are set to 2. For an external interrupt, bits 7:0 receive theinterrupt number.— Bits 10:8 are set to 0 (external interrupt), 2 (non-maskable interrupt), 3(hardware exception), or 6 (software exception).
Hardware exceptionscomprise all exceptions except breakpoint exceptions (#BP; generated byINT3) and overflow exceptions (#OF; generated by INTO); these aresoftware exceptions. Note that BOUND range exceeded exceptions (#BR;generated by BOUND) and invalid opcode exceptions (#UD) generated byUD2 are hardware exceptions.— Bit 11 is set to 1 if the VM exit is caused by a hardware exception that wouldhave delivered an error code on the stack. If bit 11 is set to 1, the error codeis placed in the VM-exit interruption error code (see below).— Bit 12 is undefined in any of the following cases:•If the “NMI exiting” VM-execution control is 1 and the “virtual NMIs”VM-execution control is 0.•If the VM exit sets the valid bit in the IDT-vectoring information field (seeSection 23.2.3).•If the VM exit is due to a double fault (the interruption type is hardwareexception and the vector is 8).Otherwise, bit 12 is defined as follows:•If the “virtual NMIs” VM-execution control is 0, the VM exit is due to afault on the IRET instruction, and blocking by NMI (see Table 20-3) was ineffect before execution of IRET, bit 12 is set to 1.Vol.
3 23-11VM EXITS•If the “virtual NMIs” VM-execution control is 1, the VM exit is due to afault on the IRET instruction, and virtual-NMI blocking was in effectbefore execution of IRET, bit 12 is set to 1.•For all other relevant VM exits, bit 12 is cleared to 0.— Bits 30:13 are always set to 0.— Bit 31 is always set to 1.For other VM exits (including those due to external interrupts when the“acknowledge interrupt on exit” VM-exit control is 0), the field is marked invalid(by clearing bit 31) and the remainder of the field is undefined.•VM-exit interruption error code.— For VM exits that set both bit 31 (valid) and bit 11 (error code valid) in theVM-exit interruption-information field, this field receives the error code thatwould have been pushed on the stack had the event causing the VM exit beendelivered normally through the IDT.
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