Volume 3B System Programming Guide_ Part 2 (794104), страница 47
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The EXT bit is set in this field exactlywhen it would be set normally. For exceptions that occur during the deliveryof double fault (if the IDT-vectoring information field indicates a double fault),the EXT bit is set to 1, assuming that (1) that the exception would produce anerror code normally (if not incident to double-fault delivery) and (2) that theerror code uses the EXT bit (not for page faults, which use a different format).— For other VM exits, the value of this field is undefined.23.2.3Information for VM Exits During Event DeliverySection 20.9.3 defined fields containing information for VM exits that occur whiledelivering an event through the IDT and as a result of either of the following cases:•A fault occurs during event delivery and causes a VM exit (because the bitassociated with the fault is set to 1 in the exception bitmap).1•A task switch is invoked through a task gate in the IDT.
Note that the VM exitoccurs due to the task switch only after the initial checks of the task switch pass(see Section 21.6.2).•Event delivery causes an APIC-access VM exit (see Section 21.2).Note that these fields are used for VM exits that occur during delivery of eventsinjected as part of VM entry (see Section 22.5.2).1. This includes the case in which a VM exit occurs while delivering a software interrupt (INT n)through the 16-bit IVT (interrupt vector table) that is used in virtual-8086 mode with virtualmachine extensions (if RFLAGS.VM = CR4.VME = 1).23-12 Vol.
3VM EXITSA VM exit is not considered to occur during event delivery in any of the followingcircumstances:•The original event causes the VM exit directly (for example, because the originalevent is a non-maskable interrupt (NMI) and the “NMI exiting” VM-executioncontrol is 1).•The original event results in a double-fault exception that causes the VM exitdirectly.•The VM exit occurred as a result of fetching the first instruction of the handlerinvoked by the event delivery.•The VM exit is caused by a triple fault.The following items detail the use of these fields:•IDT-vectoring information (format given in Table 20-14). The following itemsdetail how this field is established for VM exits that occur during event delivery:— If the VM exit occurred during delivery of an exception, bits 7:0 receive theexception vector (at most 31).
If the VM exit occurred during delivery of anNMI, bits 7:0 are set to 2. If the VM exit occurred during delivery of anexternal interrupt, bits 7:0 receive the interrupt number.— Bits 10:8 are set to indicate the type of event that was being delivered whenthe VM exit occurred: 0 (external interrupt), 2 (non-maskable interrupt), 3(hardware exception), 4 (software interrupt), 5 (privileged softwareinterrupt), or 6 (software exception).Hardware exceptions comprise all exceptions except breakpoint exceptions(#BP; generated by INT3) and overflow exceptions (#OF; generated byINTO); these are software exceptions. Note that BOUND range exceededexceptions (#BR; generated by BOUND) and invalid opcode exceptions(#UD) generated by UD2 are hardware exceptions.Bits 10:8 may indicate privileged software interrupt if such an event wasinjected as part of VM entry.— Bit 11 is set to 1 if the VM exit occurred during delivery of a hardwareexception that would have delivered an error code on the stack.
If bit 11 isset to 1, the error code is placed in the IDT-vectoring error code (see below).— Bit 12 is undefined.— Bits 30:13 are always set to 0.— Bit 31 is always set to 1.For other VM exits, the field is marked invalid (by clearing bit 31) and theremainder of the field is undefined.•IDT-vectoring error code.— For VM exits that set both bit 31 (valid) and bit 11 (error code valid) in theIDT-vectoring information field, this field receives the error code that wouldVol.
3 23-13VM EXITShave been pushed on the stack by the event that was being delivered throughthe IDT at the time of the VM exit. The EXT bit is set in this field when it wouldbe set normally.— For other VM exits, the value of this field is undefined.23.2.4Information for VM Exits Due to Instruction ExecutionSection 20.9.4 defined fields containing information for VM exits that occur due toinstruction execution. (The VM-exit instruction length is also used for VM exits thatoccur during the delivery of a software interrupt or software exception.) Thefollowing items detail their use.•VM-exit instruction length.
This field is used in the following cases:— For fault-like VM exits due to attempts to execute one of the followinginstructions that cause VM exits unconditionally (see Section 21.1.2) orbased on the settings of VM-execution controls (see Section 21.1.3): CLTS,CPUID, HLT, IN, INS INVD, INVLPG, LMSW, MONITOR, MOV CR, MOV DR,MWAIT, OUT, OUTS, PAUSE, RDMSR, RDPMC, RDTSC, RSM, VMCALL,VMCLEAR, VMLAUNCH, VMPTRLD, VMPTRST, VMREAD, VMRESUME,VMWRITE, VMXOFF, VMXON, and WRMSR.1— For VM exits due to software exceptions (those generated by executions ofINT3 or INTO).— For VM exits due to faults encountered during delivery of a softwareinterrupt, privileged software exception, or software exception.— For VM exits due to attempts to effect a task switch via instruction execution.These are VM exits that produce an exit reason indicating task switch andeither of the following:•An exit qualification indicating execution of CALL, IRET, or JMPinstruction.•An exit qualification indicating a task gate in the IDT and an IDT-vectoringinformation field indicating that the task gate was encountered duringdelivery of a software interrupt, privileged software exception, orsoftware exception.— For APIC-access VM exits resulting from linear accesses (see Section 21.2.1)and encountered during delivery of a software interrupt, privileged softwareexception, or software exception.21.
This item applies only to fault-like VM exits. It does not apply to trap-like VM exits following executions of the MOV to CR8 instruction when the “use TPR shadow” VM-execution control is 1.2. The VM-exit instruction-length field is not defined following APIC-access VM exits resulting fromphysical accesses (see Section 21.2.2) even if encountered during delivery of a software interrupt, privileged software exception, or software exception.23-14 Vol. 3VM EXITSIn all the above cases, this field receives the length in bytes (1–15) of theinstruction (including any instruction prefixes) whose execution led to theVM exit (see the next paragraph for one exception).The cases of VM exits encountered during delivery of a software interrupt,privileged software exception, or software exception include those encounteredduring delivery of events injected as part of VM entry (see Section 22.5.2).
If theoriginal event was injected as part of VM entry, this field receives the value of theVM-entry instruction length.All VM exits other than those listed in the above items leave this field undefined.•Guest linear address. For VM exits due to some instructions, this field receivesthe linear address of one of the instruction operands.— VM exits due to attempts to execute LMSW with a memory operand. In thesecases, this field receives the linear address of that operand. On processorsthat support Intel 64 architecture, bits 63:32 are cleared if the logicalprocessor was not in 64-bit mode before the VM exit.— VM exits due to attempts to execute INS or OUTS for which the relevantsegment (ES for INS; DS for OUTS unless overridden by an instruction prefix)is usable.
The field receives the value of the linear address generated byES:(E)DI (for INS) or segment:(E)SI (for OUTS; the default segment is DSbut can be overridden by a segment override prefix). (If the relevantsegment is not usable, the value is undefined.) On processors that supportIntel 64 architecture, bits 63:32 are cleared if the logical processor was not in64-bit mode before the VM exit.— For all other VM exits, the field is undefined.•VM-exit instruction information.— For VM exits due to attempts to execute VMCLEAR, VMPTRLD, VMPTRST,VMREAD, VMWRITE, or VMXON, this field receives information about theinstruction that caused the VM exit and has the format is given in Table 23-7.Table 23-7.
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