Volume 3B System Programming Guide_ Part 2 (794104), страница 45
Текст из файла (страница 45)
Nodebug exceptions are considered pending.— A page fault updates CR2.— An NMI causes subsequent NMIs to be blocked before the VM exitcommences.— An external interrupt acknowledges the interrupt controller and the interruptis no longer pending.— If the logical processor had been in an inactive state, it enters the active stateand, before the VM exit commences, generates any special bus cycle that isnormally generated when the active state is entered from that activity state.— There is no blocking by STI or by MOV SS when the VM exit commences.— Processor state that is normally updated as part of delivery through the IDT(CS, RIP, SS, RSP, RFLAGS) is not modified.
However, the incomplete deliveryof the event may write to the stack.— The treatment of last-exception records is implementation dependent:••Some processors make a last-exception record when beginning thedelivery of an event through the IDT (before it can encounter a nestedexception). Such processors perform this update even if the eventencounters a nested exception that causes a VM exit (including the casewhere nested exceptions lead to a triple fault).•Other processors delay making a last-exception record until eventdelivery has reached some event handler successfully (perhaps after oneor more nested exceptions). Such processors do not update the lastexception record if a VM exit or triple fault occurs before an event handleris reached.If the “virtual NMIs” VM-execution control is 1, VM entry injects an NMI, anddelivery of the NMI causes a nested exception, double fault, task switch, or APIC1.
If a VM exit takes the processor from an inactive state resulting from execution of a specificinstruction (HLT or MWAIT), the value saved for RIP by that VM exit will reference the followinginstruction.2. An exception is made if the logical processor had been inactive due to execution of MWAIT; inthis case, it is considered to have become active before the VM exit.Vol.
3 23-3VM EXITSaccess that causes a VM exit, virtual-NMI blocking is in effect before the VM exitcommences.•If a VM exit results from a fault encountered during execution of IRET and the“NMI exiting” VM-execution control is 0, any blocking by NMI is cleared before theVM exit commences. However, the previous state of blocking by NMI may berecorded in the VM-exit interruption-information field; see Section 23.2.2.•If a VM exit results from a fault encountered during execution of IRET and the“virtual NMIs” VM-execution control is 1, virtual-NMI blocking is cleared beforethe VM exit commences. However, the previous state of virtual-NMI blocking maybe recorded in the VM-exit interruption-information field; see Section 23.2.2.•Suppose that a VM exit is caused directly by an x87 FPU Floating-Point Error(#MF) or by any of the following events if the event was unblocked due to (andgiven priority over) an x87 FPU Floating-Point Error: an INIT signal, an externalinterrupt, an NMI, an SMI; or a machine-check exception.
In these cases, thereis no blocking by STI or by MOV SS when the VM exit commences.•Normally, a last-branch record may be made when an event is delivered throughthe IDT. However, if such an event results in a VM exit before delivery iscomplete, no last-branch record is made.•If machine-check exception results in a VM exit, processor state is suspect andmay result in suspect state being saved to the guest-state area. A VM monitorshould consult the RIPV and EIPV bits in the IA32_MCG_STATUS MSR beforeresuming a guest that caused a VM exit resulting from a machine-checkexception.•If a VM exit results from a fault encountered while executing an instruction, databreakpoints due to that instruction may have been recognized and informationabout them may be saved in the pending debug exceptions field (see Section23.3.4).•The following VM exits are considered to happen after an instruction is executed:— VM exits resulting from debug traps (single-step, I/O breakpoints, and databreakpoints).— VM exits resulting from debug exceptions whose recognition was delayed byblocking by MOV SS.— VM exits resulting from some machine-check exceptions.— Trap-like VM exits due to execution of MOV to CR8 when the “CR8-loadexiting” VM-execution control is 0 and the “use TPR shadow” VM-executioncontrol is 1.
(Such VM exits can occur only from 64-bit mode and thus only onprocessors that support Intel 64 architecture.)— VM exits caused by TPR-shadow updates (see Section 21.5.3.3) that resultfrom APIC accesses as part of instruction execution.For these VM exits, the instruction’s modifications to architectural state completebefore the VM exit occurs. Such modifications include those to the logicalprocessor’s interruptibility state (see Table 20-3). If there had been blocking by23-4 Vol. 3VM EXITSMOV SS, POP SS, or STI before the instruction executed, such blocking is nolonger in effect.23.2RECORDING VM-EXIT INFORMATION AND UPDATINGCONTROLSVM exits begin by recording information about the nature of and reason for theVM exit in the VM-exit information fields.
Section 23.2.1 to Section 23.2.4 detail theuse of these fields.In addition to updating the VM-exit information fields, the valid bit (bit 31) is clearedin the VM-entry interruption-information field.23.2.1Basic VM-Exit InformationSection 20.9.1 defines the basic VM-exit information fields. The following items detailtheir use.•Exit reason.— Bits 15:0 of this field contain the basic exit reason. It is loaded with a numberindicating the general cause of the VM exit. Appendix I lists the numbers usedand their meaning.— The remainder of the field (bits 31:16) is cleared on every VM exit.•Exit qualification. This field is saved for VM exits due to the following causes:debug exceptions; page-fault exceptions; start-up IPIs (SIPIs); systemmanagement interrupts (SMIs) that arrive immediately after the retirement ofI/O instructions; task switches; INVLPG; VMCLEAR; VMPTRLD; VMPTRST;VMREAD; VMWRITE; VMXON; control-register accesses; MOV DR; I/O instructions; MWAIT; and accesses to the APIC-access page (see Section 21.2).
For allother VM exits, this field is cleared. The following items provide details:— For debug exceptions, the exit qualification contains information about thedebug exception. The information has the format given in Table 23-1.Table 23-1. Exit Qualification for Debug ExceptionsBit Position(s)Contents3:0B3 – B0. When set, each of these bits indicates that the correspondingbreakpoint condition was met.
Any of these bits may be set even if itscorresponding enabling bit in DR7 is not set.12:4Reserved (cleared to 0).Vol. 3 23-5VM EXITSTable 23-1. Exit Qualification for Debug Exceptions (Contd.)Bit Position(s)Contents13BD. When set, this bit indicates that the cause of the debug exception is“debug register access detected.”14BS. When set, this bit indicates that the cause of the debug exception iseither the execution of a single instruction (if RFLAGS.TF = 1 andIA32_DEBUGCTL.BTF = 0) or a taken branch (ifRFLAGS.TF = DEBUGCTL.BTF = 1).63:15Reserved (cleared to 0).
Bits 63:32 exist only on processors thatsupport Intel 64 architecture.— For page-fault exceptions, the exit qualification contains the linear addressthat caused the page fault. On processors that support Intel 64 architecture,bits 63:32 are cleared if the logical processor was not in 64-bit mode beforethe VM exit.— Start-up IPI (SIPI). The SIPI vector information is stored in bits 7:0 of theexit qualification. Bits 63:8 are cleared to 0.— Task switch. Details about the reason for the VM exit are encoded as shown inTable 23-2.Table 23-2. Exit Qualification for Task SwitchBit Position(s)Contents15:0Selector of task-state segment (TSS) to which the guest attempted to switch29:16Reserved (cleared to 0)31:30Source of task switch initiation:0: CALL instruction1: IRET instruction2: JMP instruction3: Task gate in IDT63:32Reserved (cleared to 0). These bits exist only on processors that support Intel64 architecture.— For INVLPG, the exit qualification contains the linear-address operand of theinstruction.•23-6 Vol.
3On processors that support Intel 64 architecture, bits 63:32 are cleared ifthe logical processor was not in 64-bit mode before the VM exit.VM EXITS•If the INVLPG source operand specifies an unusable segment, the linearaddress specified in the exit qualification will match the linear addressthat the INVLPG would have used if no VM exit occurred. Note that thisaddress is not architecturally defined and may be implementationspecific.— VMCLEAR, VMPTRLD, VMPTRST, VMREAD, VMWRITE, VMXON. The exit qualification receives the value of the instruction’s displacement field, which issign-extended to 64 bits if necessary (32 bits on processors that do notsupport Intel 64 architecture).
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