Volume 3B System Programming Guide_ Part 2 (794104), страница 40
Текст из файла (страница 40)
The Type must be 2 (LDT).Bit 4 (S). S must be 0.Bit 7 (P). P must be 1.Bits 11:8 (reserved). These bits must all be 0.Bit 15 (G).— If any bit in the limit field in the range 11:0 is 0, G must be 0.— If any bit in the limit field in the range 31:20 is 1, G must be 1.•22.3.1.3Bits 31:17 (reserved). These bits must all be 0.Checks on Guest Descriptor-Table RegistersThe following checks are performed on the fields for GDTR and IDTR:•On processors that support Intel 64 architecture, the base-address fields mustcontain canonical addresses.•Bits 31:16 of each limit field must be 0.22.3.1.4Checks on Guest RIP and RFLAGSThe following checks are performed on fields in the guest-state area corresponding toRIP and RFLAGS:•RIP. The following checks are performed on processors that support Intel 64architecture:— Bits 63:32 must be 0 if the “IA-32e mode guest” VM-entry control is 0 or ifthe L bit (bit 13) in the access-rights field for CS is 0.— If the processor supports N < 64 linear-address bits, bits 63:N must beidentical if the “IA-32e mode guest” VM-entry control is 1 and the L bit in the22-12 Vol.
3VM ENTRIESaccess-rights field for CS is 1.1 (No check applies if the processor supports 64linear-address bits.)•RFLAGS.— Reserved bits 63:22 (bits 31:22 on processors that do not support Intel 64architecture), bit 15, bit 5 and bit 3 must be 0 in the field, and reserved bit 1must be 1.— On processors that support Intel 64 architecture, the VM flag (bit 17) must be0 if the “IA-32e mode guest” VM-entry control is 1.— The IF flag (RFLAGS[bit 9]) must be 1 if the valid bit (bit 31) in the VM-entryinterruption-information field is 1 and the interruption type (bits 10:8) isexternal interrupt.22.3.1.5Checks on Guest Non-Register StateThe following checks are performed on fields in the guest-state area corresponding tonon-register state:•Activity state.— The activity-state field must contain a value in the range 0 – 3, indicating anactivity state supported by the implementation (see Section 20.4.2).
Futureprocessors may include support for other activity states. Software shouldread the VMX capability MSR IA32_VMX_MISC (see Appendix G.5) todetermine what activity states are supported.— The activity-state field must not indicate the HLT state if the DPL (bits 6:5) inthe access-rights field for SS is not 0.2— The activity-state field must indicate the active state if the interruptibilitystate field indicates blocking by either MOV-SS or by STI (if either bit 0 orbit 1 in that field is 1).— If the valid bit (bit 31) in the VM-entry interruption-information field is 1, theinterruption to be delivered (as defined by interruption type and vector) mustnot be one that would normally be blocked while a logical processor is in theactivity state corresponding to the contents of the activity-state field.
Thefollowing items enumerate the interruptions whose injection is allowed for thedifferent activity states:••Active. Any interruption is allowed.HLT. The only events allowed are those with interruption type externalinterrupt or non-maskable interrupt (NMI) and those with interruption1. Software can determine the number N by executing CPUID with 80000008H in EAX. The number of linear-address bits supported is returned in bits 15:8 of EAX.2. As noted in Section 20.4.1, SS.DPL corresponds to the logical processor’s current privilege level(CPL).Vol.
3 22-13VM ENTRIEStype hardware exception and vector 1 (debug exception) or vector 18(machine-check exception).••Shutdown. Only NMIs and machine-check exceptions are allowed.Wait-for-SIPI. No interruptions are allowed.— The activity-state field must not indicate the wait-for-SIPI state if the “entryto SMM” VM-entry control is 1.•Interruptibility state.— The reserved bits (bits 31:4) must be 0.— The field cannot indicate blocking by both STI and MOV SS (bits 0 and 1cannot both be 1).— Bit 0 (blocking by STI) must be 0 if the IF flag (bit 9) is 0 in the RFLAGS field.— Bit 0 (blocking by STI) and bit 1 (blocking by MOV-SS) must both be 0 if thevalid bit (bit 31) in the VM-entry interruption-information field is 1 and theinterruption type (bits 10:8) in that field has value 0, indicating externalinterrupt.— Bit 1 (blocking by MOV-SS) must be 0 if the valid bit (bit 31) in the VM-entryinterruption-information field is 1 and the interruption type (bits 10:8) in thatfield has value 2, indicating non-maskable interrupt (NMI).— Bit 2 (blocking by SMI) must be 0 if the processor is not in SMM.— Bit 2 (blocking by SMI) must be 1 if the “entry to SMM” VM-entry control is 1.— A processor may require bit 0 (blocking by STI) to be 0 if the valid bit (bit 31)in the VM-entry interruption-information field is 1 and the interruption type(bits 10:8) in that field has value 2, indicating NMI.
Other processors may notmake this requirement.— Bit 3 (blocking by NMI) must be 0 if the “virtual NMIs” VM-execution controlis 1, the valid bit (bit 31) in the VM-entry interruption-information field is 1,and the interruption type (bits 10:8) in that field has value 2 (indicatingNMI).NOTEIf the “virtual NMIs” VM-execution control is 0, there is norequirement that bit 3 be 0 if the valid bit in the VM-entryinterruption-information field is 1 and the interruption type in thatfield has value 2.•Pending debug exceptions.— Bits 11:4, bit 13, and bits 63:15 (bits 31:15 on processors that do notsupport Intel 64 architecture) must be 0.— The following checks are performed if any of the following holds: (1) theinterruptibility-state field indicates blocking by STI (bit 0 in that field is 1);22-14 Vol.
3VM ENTRIES(2) the interruptibility-state field indicates blocking by MOV SS (bit 1 in thatfield is 1); or (3) the activity-state field indicates HLT:••Bit 14 (BS) must be 1 if the TF flag (bit 8) in the RFLAGS field is 1 and theBTF flag (bit 1) in the IA32_DEBUGCTL field is 0.•Bit 14 (BS) must be 0 if the TF flag (bit 8) in the RFLAGS field is 0 or theBTF flag (bit 1) in the IA32_DEBUGCTL field is 1.VMCS link pointer. The following checks apply if the field contains a value otherthan FFFFFFFF_FFFFFFFFH:— Bits 11:0 must be 0.— On processors that support Intel 64 architecture, bits beyond the processor’sphysical-address width must be 0.1 On processors that do not support Intel64 architecture, bits in the range 63:32 must be 0.— The 32 bits located in memory referenced by the value of the field (as aphysical address) must contain the processor’s VMCS revision identifier (seeSection 20.2).— If the processor is not in SMM or the “entry to SMM” VM-entry control is 1, thefield must not contain the current VMCS pointer.— If the processor is in SMM and the “entry to SMM” VM-entry control is 0, thefield must not contain the VMXON pointer.22.3.1.6Checks on Guest Page-Directory PointersIf bit 5 in CR4 (CR4.PAE) is 1, the logical processor uses the physical-addressextension (PAE).
If IA32_EFER.LMA is 0, the logical processor also uses PAEpaging (see Section 3.8 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A).2 When PAE paging is in use, the physical address in CR3references a table of page-directory pointers (PDPTRs). A MOV to CR3 when PAEpaging is in use checks the validity of these pointers.A VM entry is to a guest that uses PAE paging if (1) bit 5 (corresponding to CR4.PAE)is set in the CR4 field in the guest-state area; and (2) the “IA-32e mode guest”VM-entry control is 0.
Such a VM entry may check the validity of the PDPTRs referenced by the CR3 field in the guest-state area. Such a VM entry must check theirvalidity if either (1) PAE paging was not in use before the VM entry; or (2) the valueof CR3 is changing as a result of the VM entry. A VM entry to a guest that does notuse PAE paging must not check the validity of the PDPTRs.1. Software can determine a processor’s physical-address width by executing CPUID with80000008H in EAX.
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