Volume 3B System Programming Guide_ Part 2 (794104), страница 50
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In particular, CS and TR are never loadedwith zero and are thus never unusable. SS can be loaded with zero only onprocessors that support Intel 64 architecture and only if the VM exit is to 64-bitmode (64-bit mode allows use of segments marked unusable).•The base address is set as follows:— CS. Cleared to zero.— SS, DS, and ES. Undefined if the segment is unusable; otherwise, cleared tozero.Vol. 3 23-25VM EXITS— FS and GS. Undefined (but, on processors that support Intel 64 architecture,canonical) if the segment is unusable and the VM exit is not to 64-bit mode;otherwise, loaded from the base-address field. Note that, on processors thatsupport Intel 64 architecture, the values loaded for base addresses for FS andGS are also manifest in the FS.base and GS.base MSRs.— TR.
Loaded from the host-state area.•The segment limit is set as follows:— CS. Set to FFFFFFFFH (corresponding to a descriptor limit of FFFFFH and a Gbit setting of 1).— SS, DS, ES, FS, and GS. Undefined if the segment is unusable; otherwise, setto FFFFFFFFH.— TR.
Set to 00000067H.•The type field and S bit are set as follows:— CS. Type set to 11 and S set to 1 (execute/read, accessed, non-conformingcode segment).— SS, DS, ES, FS, and GS. Undefined if the segment is unusable; otherwise,type set to 3 and S set to 1 (read/write, accessed, expand-up data segment).— TR. Type set to 11 and S set to 0 (busy 32-bit task-state segment).•The DPL is set as follows:— CS, SS, and TR. Set to 0. The current privilege level (CPL) will be 0 after theVM exit completes.— DS, ES, FS, and GS. Undefined if the segment is unusable; otherwise, set to0.•The P bit is set as follows:— CS, TR. Set to 1.— SS, DS, ES, FS, and GS. Undefined if the segment is unusable; otherwise, setto 1.•On processors that support Intel 64 architecture, CS.L is loaded with the settingof the “host address-space size” VM-exit control.
Because this control is alsoloaded into IA32_EFER.LMA (see Section 23.5.1), no VM exit is ever to compatibility mode (which requires IA32_EFER.LMA = 1 and CS.L = 0).•D/B.— CS. Loaded with the inverse of the setting of the “host address-space size”VM-exit control. For example, if that control is 0, indicating a 32-bit guest,CS.D/B is set to 1.— SS, DS, ES, FS, and GS. Undefined if the segment is unusable; otherwise, setto 1.— TR.
Set to 0.23-26 Vol. 3VM EXITS•G.— CS. Set to 1.— SS, DS, ES, FS, and GS. Undefined if the segment is unusable; otherwise, setto 1.— TR. Set to 0.The host-state area does not contain a selector field for LDTR. LDTR is established asfollows on all VM exits: the selector is cleared to 0000H, the segment is markedunusable and is otherwise undefined (although the base address is always canonical).The base addresses for GDTR and IDTR are loaded from the GDTR base-address fieldand the IDTR base-address field, respectively. The GDTR and IDTR limits are each setto FFFFH.23.5.3Loading Host RIP, RSP, and RFLAGSRIP and RSP are loaded from the RIP field and the RSP field, respectively.
RFLAGS iscleared, except bit 1, which is always set.23.5.4Checking and Loading Host Page-Directory PointersIf bit 5 in CR4 (CR4.PAE) is 1, the logical processor uses the physical-addressextension (PAE). If, in addition, IA32_EFER.LMA is 0, the logical processor uses PAEpaging. See Section 3.8 of the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A.1 When in PAE paging is in use, the physical address inCR3 references a table of page-directory pointers (PDPTRs).
A MOV to CR3 whenPAE paging is in use checks the validity of these pointers and, if they are valid, loadsthem into the processor (into internal, non-architectural registers).A VM exit is to a VMM that uses PAE paging if (1) bit 5 (corresponding to CR4.PAE) isset in the CR4 field in the host-state area of the VMCS; and (2) the “host addressspace size” VM-exit control is 0.
Such a VM exit may check the validity of the PDPTRsreferenced by the CR3 field in the host-state area of the VMCS. Such a VM exit mustcheck their validity if either (1) PAE paging was not in use before the VM exit; or(2) the value of CR3 is changing as a result of the VM exit. A VM exit to a VMM thatdoes not use PAE paging must not check the validity of the PDPTRs.A VM exit that checks the validity of the PDPTRs uses the same checks that are usedwhen CR3 is loaded with MOV to CR3 when PAE paging is in use. If MOV to CR3 wouldcause a general-protection exception due to the PDPTRs that would be loaded (e.g.,1.
On processors that support Intel 64 architecture, the physical-address extension may supportmore than 36 physical-address bits. Software can determine a processor’s physical-addresswidth by executing CPUID with 80000008H in EAX. The physical-address width is returned inbits 7:0 of EAX.Vol. 3 23-27VM EXITSbecause a reserved bit is set), a VMX abort occurs (see Section 23.7).
If a VM exit toa VMM that uses PAE does not cause a VMX abort, the PDPTRs are loaded into theprocessor as would MOV to CR3, using the value of CR3 being load by the VM exit.23.5.5Updating Non-Register StateVM exits affect the non-register state of a logical processor as follows:••A logical processor is always in the active state after a VM exit.Event blocking is affected as follows:— There is no blocking by STI or by MOV SS after a VM exit.— VM exits caused directly by non-maskable interrupts (NMIs) cause blockingby NMI (see Table 20-3). Other VM exits do not affect blocking by NMI. (SeeSection 23.1 for the case in which an NMI causes a VM exit indirectly.)•There are no pending debug exceptions after a VM exit.23.5.6Clearing Address-Range MonitoringThe Intel 64 and IA-32 architectures allow software to monitor a specified addressrange using the MONITOR and MWAIT instructions.
See Section 7.11.4 in the Intel®64 and IA-32 Architectures Software Developer’s Manual, Volume 3A. VM exits clearany address-range monitoring that may be in effect.23.6LOADING MSRSVM exits may load MSRs from the VM-exit MSR-load area (see Section 20.7.2).Specifically each entry in that area (up to the number specified in the VM-exit MSRload count) is processed in order by loading the MSR indexed by bits 31:0 with thecontents of bits 127:64 as they would be written by WRMSR.Processing of an entry fails in any of the following cases:•The value of bits 31:0 is either C0000100H (the IA32_FS_BASE MSR) orC0000101H (the IA32_GS_BASE MSR).•The value of bits 31:0 indicates an MSR that can be read only in systemmanagement mode (SMM) and the VM exit will not end in SMM.(IA32_SMM_MONITOR_CTL is an MSR that can be written only in SMM.)•The value of bits 31:0 indicates an MSR that cannot be loaded on VM exits formodel-specific reasons.
A processor may prevent loading of certain MSRs even ifthey can normally be written by WRMSR. Such model-specific behavior isdocumented in Appendix B.•Bits 63:32 are not all 0.23-28 Vol. 3VM EXITS•An attempt to write bits 127:64 to the MSR indexed by bits 31:0 of the entrywould cause a general-protection exception if executed via WRMSR withCPL = 0.1If processing fails for any entry, a VMX abort occurs. See Section 23.7.If any MSR is being loaded in such a way that would architecturally require a TLBflush, the TLBs are updated so that, after VM exit, the logical processor does not useany translations that were cached before the transition.23.7VMX ABORTSA problem encountered during a VM exit leads to a VMX abort.
A VMX abort takes alogical processor into a shutdown state as described below.A VMX abort does not modify the VMCS data in the VMCS region of any active VMCS.The contents of these data are thus suspect after the VMX abort.On a VMX abort, a logical processor saves a nonzero 32-bit VMX-abort indicator fieldat byte offset 4 in the VMCS region of the VMCS whose misconfiguration caused thefailure (see Section 20.2).
The following values are used:1. There was a failure in saving guest MSRs (see Section 23.4).2. Host checking of the page-directory pointers (PDPTRs) failed (see Section23.5.4).3. The current VMCS has been corrupted (through writes to the correspondingVMCS region) in such a way that the logical processor cannot complete theVM exit properly.4. There was a failure on loading host MSRs (see Section 23.6).5. There was a machine check during VM exit (see Section 23.8).Some of these causes correspond to failures during the loading of state from thehost-state area. Because the loading of such state may be done in any order (seeSection 23.5) a VM exit that might lead to a VMX abort for multiple reasons (forexample, the current VMCS may be corrupt and the host PDPTRs might not be properly configured). In such cases, the VMX-abort indicator could correspond to any oneof those reasons.A logical processor never reads the VMX-abort indicator in a VMCS region and writesit only with one of the non-zero values mentioned above.
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